公开(公告)号：US20180365368A1

公开(公告)日：2018-12-20

申请号：US15933958

申请日：2018-03-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-ho DO ,  Jong-hoon JUNG ,  Ji-su YU ,  Seung-young LEE ,  Tae-joong SONG ,  Jae-boong LEE

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5072 ,  H01L27/0207 ,  H01L27/11807

Abstract: Provided is an integrated circuit including a plurality of standard cells each including a front-end-of-line (FEOL) region and a back-end-of-line (BEOL) region on the FEOL region, the FEOL region including at least one gate line extending in a first horizontal direction. A BEOL region of a first standard cell among the plurality of standard cells includes an eaves section not overlapping an FEOL region of the first standard cell in a vertical direction, the eaves section protruding in a second horizontal direction perpendicular to the first horizontal direction.

公开(公告)号：US20170221818A1

公开(公告)日：2017-08-03

申请号：US15493279

申请日：2017-04-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Vincent Chun Fai LAU ,  Jung-ho DO ,  Byung-sung KIM ,  Chul-hong PARK

IPC: H01L23/522 ,  H01L23/528 ,  H01L27/02 ,  H01L27/088

CPC classification number: H01L23/5226 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/11807 ,  H01L2027/11874 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a substrate; a plurality of conductive areas formed on the substrate at a first vertical level; a first wiring layer formed on the substrate at a second vertical level which is higher than the first vertical level, the first wiring layer including first lines that extend in a first direction, one first line of the first lines connected to a first conductive area selected from the plurality of conductive areas through a via contact; a second wiring layer formed on the substrate at a third vertical level which is higher than the second vertical level, the second wiring layer including second lines that extend in a second direction that crosses the first direction, one second line of the second lines connected to a second conductive area selected from the plurality of conductive areas; and a deep via contact spaced apart from lines of the first wiring layer in a horizontal direction and extending from the second conductive area to the one second line.

公开(公告)号：US20180175024A1

公开(公告)日：2018-06-21

申请号：US15686795

申请日：2017-08-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-ho DO ,  Sang-hoon Baek ,  Tae-joong Song ,  Jong-hoon Jung ,  Seung-young Lee

IPC: H01L27/088 ,  H01L23/528 ,  H01L29/78 ,  H01L27/07 ,  H01L27/02 ,  H01L29/417 ,  H01L23/522

CPC classification number: H01L27/088 ,  H01L21/823487 ,  H01L21/823885 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/0705 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/41741 ,  H01L29/7827

Abstract: An integrated circuit having a vertical transistor includes first through fourth gate lines extending in a first direction and sequentially arranged in parallel with each other, a first top active region over the first through third gate lines and insulated from the second gate line, and a second top active region. The first top active region forms first and third transistors with the first and third gate lines respectively. The second top active region is over the second through fourth gate lines and insulated from the third gate line. The second top active region forms second and fourth transistors with the second and fourth gate lines respectively.

公开(公告)号：US20210013230A1

公开(公告)日：2021-01-14

申请号：US17034602

申请日：2020-09-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-ho DO ,  Ji-Su YU ,  Hyeon-gyu YOU ,  Seung-Young LEE ,  Jae-boong LEE ,  Jong-hoon JUNG

IPC: H01L27/118 ,  H01L27/02

Abstract: An integrated circuit includes a standard cell. The standard cell may include a plurality of gate lines and a plurality of first wirings. The plurality of first wirings may include a clubfoot structure conductive pattern that includes a first conductive pattern and a second conductive pattern spaced apart from each other. Each of the first conductive pattern and the second conductive pattern may include a first line pattern extending in a first direction and a second line pattern protruding from one end of the first line pattern in a direction perpendicular to the first direction. The plurality of gate lines may be spaced apart from each other by a first pitch in the first direction, and the plurality of second wirings may be spaced apart from each other by a second pitch in the first direction. The first pitch may be greater than the second pitch.

公开(公告)号：US20200159984A1

公开(公告)日：2020-05-21

申请号：US16750501

申请日：2020-01-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-ho DO ,  Jong-hoon JUNG ,  Ji-Su YU ,  Seung-young LEE ,  Tae-joong SONG ,  Jae-boong LEE

IPC: G06F30/398 ,  H01L27/118 ,  H01L27/02 ,  G06F30/392

Abstract: Provided is an integrated circuit including a plurality of standard cells each including a front-end-of-line (FEOL) region and a back-end-of-line (BEOL) region on the FEOL region, the FEOL region including at least one gate line extending in a first horizontal direction. A BEOL region of a first standard cell among the plurality of standard cells includes an eaves section not overlapping an FEOL region of the first standard cell in a vertical direction, the eaves section protruding in a second horizontal direction perpendicular to the first horizontal direction.

公开(公告)号：US20190181130A1

公开(公告)日：2019-06-13

申请号：US16203845

申请日：2018-11-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-ho DO

IPC: H01L27/02 ,  G06F17/50

Abstract: Provided are integrated circuits including a plurality of standard cells aligned along a plurality of rows. The integrated circuit includes first standard cells aligned on the first row and including first conductive patterns to which a first supply voltage is applied in a conductive layer and second standard cells aligned on the second row which is adjacent to the first row in the conductive layer and including second conductive patterns to which the first supply voltage is applied in the conductive layer. A pitch between the first conductive patterns and the second conductive patterns may be less than a pitch provided by single-patterning.

公开(公告)号：US20210028160A1

公开(公告)日：2021-01-28

申请号：US17038292

申请日：2020-09-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung-Young LEE ,  Jong-hoon JUNG ,  Myoung-ho KANG ,  Jung-ho DO

IPC: H01L27/02 ,  G11C11/419 ,  G11C11/40 ,  H01L23/528 ,  H01L27/105 ,  H01L27/118

Abstract: In one embodiment, the standard cell includes first and second active regions defining an intermediate region between the first and second active regions; and first, second and third gate lines crossing the first and second active regions and crossing the intermediate region. The first gate line is divided into an upper first gate line and a lower first gate line by a first gap insulating layer in the intermediate region, the second gate line is undivided, and the third gate line is divided into an upper third gate line and a lower third gate line by a second gap insulating layer in the intermediate region.

公开(公告)号：US20190109088A1

公开(公告)日：2019-04-11

申请号：US16200747

申请日：2018-11-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Vincent Chun Fai LAU ,  Jung-ho DO ,  Byung-sung KIM ,  Chul-hong PARK

IPC: H01L23/522 ,  H01L23/528 ,  H01L27/118 ,  H01L27/088 ,  H01L27/02

CPC classification number: H01L23/5226 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/11807 ,  H01L2027/11874 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a substrate; a plurality of conductive areas formed on the substrate at a first vertical level; a first wiring layer formed on the substrate at a second vertical level which is higher than the first vertical level, the first wiring layer including first lines that extend in a first direction, one first line of the first lines connected to a first conductive area selected from the plurality of conductive areas through a via contact; a second wiring layer formed on the substrate at a third vertical level which is higher than the second vertical level, the second wiring layer including second lines that extend in a second direction that crosses the first direction, one second line of the second lines connected to a second conductive area selected from the plurality of conductive areas; and a deep via contact spaced apart from lines of the first wiring layer in a horizontal direction and extending from the second conductive area to the one second line.

公开(公告)号：US20180108646A1

公开(公告)日：2018-04-19

申请号：US15674931

申请日：2017-08-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung-young LEE ,  Jong-hoon JUNG ,  Myoung-ho KANG ,  Jung-ho DO

IPC: H01L27/02 ,  G11C11/40 ,  H01L27/105 ,  H01L27/118 ,  H01L23/528

Abstract: In one embodiment, the standard cell includes first and second active regions defining an intermediate region between the first and second active regions; and first, second and third gate lines crossing the first and second active regions and crossing the intermediate region. The first gate line is divided into an upper first gate line and a lower first gate line by a first gap insulating layer in the intermediate region, the second gate line is undivided, and the third gate line is divided into an upper third gate line and a lower third gate line by a second gap insulating layer in the intermediate region.