公开(公告)号：US12155743B2

公开(公告)日：2024-11-26

申请号：US17957414

申请日：2022-09-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunggeun Kim ,  Nakwon Lee ,  Jaehyun Park ,  Kyeongjoon Ko ,  Kangjik Kim ,  Seuk Son ,  Byunghyun Lim

IPC: H04L7/00

Abstract: A clock data recovery circuit includes an inphase-quadrature (I-Q) merged phase interpolator circuit configured to generate a first clock pair and a second clock pair from a plurality of reference clock signals, the plurality of reference clock signals having different phases, the first clock pair comprising an I clock signal and an inverted I clock signal, and the second clock pair comprising a Q clock signal and an inverted Q clock signal, a sampler circuit configured to sample input data based on the first clock pair and the second clock pair, and a control circuit configured to control phases of the first clock pair and the second clock pair, the controlling including providing a control signal to the I-Q merged phase interpolator circuit based on a sampling result of the sampler circuit, the I-Q merged phase interpolator circuit is configured to share analog inputs based on the control signal.