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    Summing circuit and equalizer including the same
    1.
    发明授权
    Summing circuit and equalizer including the same 有权

    公开(公告)号：US11870615B2

    公开(公告)日：2024-01-09

    申请号：US17835373

    申请日：2022-06-08

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kyeongjoon Ko ,  Jaehyun Park ,  Junhan Bae ,  Gyeongseok Song ,  Jongjae Ryu

    IPC: H04L25/03 ,  H03K3/037 ,  H03K19/20

    CPC classification number: H04L25/03057 ,  H03K3/037 ,  H03K19/20

    Abstract: Provided are a summing circuit and an equalizer including the summing circuit. The summing circuit includes: a reference signal generator generating a first reference signal and a second reference signal, based on a coefficient code; a first non-overlap clock buffer generating a first switching signal and a second switching signal by using the first reference signal; and a first current source receiving the first switching signal and the second switching signal generated by the first non-overlap clock buffer, generating a first output current by using a bias voltage, and outputting the first output current to an output line, wherein the first switching signal includes a switching signal and a complementary switching signal that is a complementary signal to the switching signal, and wherein a logic low period of the second switching signal is included in a logic high period of the complementary switching signal of the first switching signal.

    Clock data recovery circuit and apparatus including the same
    8.
    发明授权
    Clock data recovery circuit and apparatus including the same 有权

    公开(公告)号：US12155743B2

    公开(公告)日：2024-11-26

    申请号：US17957414

    申请日：2022-09-30

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sunggeun Kim ,  Nakwon Lee ,  Jaehyun Park ,  Kyeongjoon Ko ,  Kangjik Kim ,  Seuk Son ,  Byunghyun Lim

    IPC: H04L7/00

    Abstract: A clock data recovery circuit includes an inphase-quadrature (I-Q) merged phase interpolator circuit configured to generate a first clock pair and a second clock pair from a plurality of reference clock signals, the plurality of reference clock signals having different phases, the first clock pair comprising an I clock signal and an inverted I clock signal, and the second clock pair comprising a Q clock signal and an inverted Q clock signal, a sampler circuit configured to sample input data based on the first clock pair and the second clock pair, and a control circuit configured to control phases of the first clock pair and the second clock pair, the controlling including providing a control signal to the I-Q merged phase interpolator circuit based on a sampling result of the sampler circuit, the I-Q merged phase interpolator circuit is configured to share analog inputs based on the control signal.

    LATCH CIRCUIT AND EQUALIZER INCLUDING THE SAME
    9.
    发明申请
    LATCH CIRCUIT AND EQUALIZER INCLUDING THE SAME 有权

    公开(公告)号：US20220400035A1

    公开(公告)日：2022-12-15

    申请号：US17834563

    申请日：2022-06-07

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kyeongjoon Ko ,  Hanseok Kim ,  Jaehyun Park ,  Junhan Bae ,  Gyeongseok Song ,  Jongjae Ryu

    IPC: H04L25/03 ,  H04B1/16

    Abstract: A latch circuit and an equalizer including the same are provided. The equalizer includes: an even data path configured to receive a reception data signal and including a first summing circuit and a first latch circuit; and an odd data path configured to receive the reception data signal and including a second summing circuit and a second latch circuit. An even data signal output from the first latch circuit is configured to be input to the second summing circuit, and an odd data signal output from the second latch circuit is configured to be input to the first summing circuit. Each of the first latch circuit and the second latch circuit includes a latch and a multiplexer.

    INTEGRATED CIRCUIT INCLUDING HIGH-SPEED DEVICE
    10.
    发明申请
    INTEGRATED CIRCUIT INCLUDING HIGH-SPEED DEVICE 有权

    公开(公告)号：US20220399266A1

    公开(公告)日：2022-12-15

    申请号：US17837786

    申请日：2022-06-10

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Gyeongseok Song ,  Kyeongjoon Ko ,  Jaehyun Park ,  Junhan Bae ,  Jongjae Ryu ,  Nakwon Lee

    IPC: H01L23/528 ,  H01L27/088

    Abstract: An integrated circuit is provided. The integrated circuit includes: an active region extending in a first direction; gate electrodes extending in a second direction in parallel with each other; source/drain regions provided on the active region between the gate electrodes; a first gate contact connected to the gate electrodes and extending in the first direction; a first gate wiring pattern provided in a first wiring layer, electrically connected to the gate electrodes through the first gate contact, and overlapping the first gate contact along a third direction perpendicular to the first and second directions; and source/drain wiring patterns provided in a second wiring layer, electrically connected to the source/drain regions, respectively, extending in parallel with the second direction, and overlapping the source/drain regions along the third direction, the second wiring layer being provided on the first wiring layer.

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