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1.发明公开公开(公告)号：US20230141322A1
公开(公告)日：2023-05-11
申请号：US17985193
申请日：2022-11-11
Applicant: Samsung Electronics Co., Ltd.
Inventor： Juyun Lee , Sunggeun Kim , Hyeonju Lee , Seuk Son , Kangjik Kim , Jaehyun Park
CPC classification number: H03L7/0807 , H03L7/089 , H03L7/093 , H03L7/0998
Abstract: A clock data recovery circuit includes a bang bang phase detector receiving data and a clock signal and determining whether a phase of the clock signal leads or lags a phase of the data, a digital loop filter receiving an output of the bang bang phase detector and filtering input jitter, an accumulator accumulating an output from the digital loop filter, an encoder encoding an output of the accumulator to generate a phase interpolation code, and a phase interpolator configured to generate the clock signal with an output phase in accordance with the phase interpolation code. The digital loop filter comprises a first sigma delta modulation (SDM) arithmetic block circuit connected to the bang bang phase detector.
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Patent Agency Ranking
公开(公告)号：US12155743B2
公开(公告)日：2024-11-26
申请号：US17957414
申请日：2022-09-30
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sunggeun Kim , Nakwon Lee , Jaehyun Park , Kyeongjoon Ko , Kangjik Kim , Seuk Son , Byunghyun Lim
IPC: H04L7/00
Abstract: A clock data recovery circuit includes an inphase-quadrature (I-Q) merged phase interpolator circuit configured to generate a first clock pair and a second clock pair from a plurality of reference clock signals, the plurality of reference clock signals having different phases, the first clock pair comprising an I clock signal and an inverted I clock signal, and the second clock pair comprising a Q clock signal and an inverted Q clock signal, a sampler circuit configured to sample input data based on the first clock pair and the second clock pair, and a control circuit configured to control phases of the first clock pair and the second clock pair, the controlling including providing a control signal to the I-Q merged phase interpolator circuit based on a sampling result of the sampler circuit, the I-Q merged phase interpolator circuit is configured to share analog inputs based on the control signal.
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公开(公告)号：US11838398B2
公开(公告)日：2023-12-05
申请号：US18051138
申请日：2022-10-31
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hyeonju Lee , Jiyoung Kim , Jaehyun Park , Seuk Son , Sooeun Lee , Dongchul Choi
CPC classification number: H04L7/033 , H03K3/037 , H03K5/26 , H03K2005/00286
Abstract: A semiconductor device includes: a data sampler configured to receive a data signal having a first frequency and to sample the data signal with a clock signal having a second frequency, higher than the first frequency, to output data for a time corresponding to a unit interval of the data signal; an error sampler configured to sample the data signal with an error clock signal having the second frequency and a phase, different from a phase of the clock signal, to output a plurality of pieces of error data for the time corresponding to the unit interval; and an eye-opening monitor (EOM) circuit configured to compare the data with each of the plurality of pieces of error data to obtain an eye diagram of the data signal in the unit interval.
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公开(公告)号：US12068752B2
公开(公告)日：2024-08-20
申请号：US17985193
申请日：2022-11-11
Applicant: Samsung Electronics Co., Ltd.
Inventor： Juyun Lee , Sunggeun Kim , Hyeonju Lee , Seuk Son , Kangjik Kim , Jaehyun Park
CPC classification number: H03L7/0807 , H03L7/089 , H03L7/093 , H03L7/0998
Abstract: A clock data recovery circuit includes a bang bang phase detector receiving data and a clock signal and determining whether a phase of the clock signal leads or lags a phase of the data, a digital loop filter receiving an output of the bang bang phase detector and filtering input jitter, an accumulator accumulating an output from the digital loop filter, an encoder encoding an output of the accumulator to generate a phase interpolation code, and a phase interpolator configured to generate the clock signal with an output phase in accordance with the phase interpolation code. The digital loop filter comprises a first sigma delta modulation (SDM) arithmetic block circuit connected to the bang bang phase detector.
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公开(公告)号：US11757437B2
公开(公告)日：2023-09-12
申请号：US17463617
申请日：2021-09-01
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Seuk Son , Hobin Song , Nakwon Lee
CPC classification number: H03K5/01 , G06F1/06 , H03K19/21 , H03M7/165 , H03K2005/00058
Abstract: A phase interpolator includes a decoder, a digital-to-analog converter (DAC), and a phase mixer. The decoder generates first and second thermometer codes and a selection signal based on a code. The DAC includes unit cells, determines two of weight signals as first and second target weight signals based on the selection signal, and adjusts a current of the first and second target weight signals by controlling the unit cells based on the first and second thermometer codes and the selection signal. The phase mixer determines two of input clock signals as first and second target clock signals and generates an output clock signal based on the first and second target weight signals and the first and second target clock signals. A phase of the output clock signal is between phases of the first and second target clock signals. The unit cells include different first and second unit cells.
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公开(公告)号：US11740270B2
公开(公告)日：2023-08-29
申请号：US17943551
申请日：2022-09-13
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Juyun Lee , Hanseok Kim , Jiyoung Kim , Jaehyun Park , Hyeonju Lee , Kangjik Kim , Sunggeun Kim , Seuk Son , Hobin Song , Nakwon Lee
CPC classification number: G01R25/04 , H03L7/085 , H03L7/0807
Abstract: An apparatus for generating an output signal having a waveform that is repeated every period, includes a storage configured to store values corresponding to the waveform in a portion of a period of the output signal, a counter configured to generate a first index of a sample included in the output signal, a controller configured to generate at least one control signal based on the first index and the period of the output signal, and a calculation circuit configured to generate the output signal by calculating an output from the storage based on the at least one control signal.
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