公开(公告)号：US20210399019A1

公开(公告)日：2021-12-23

申请号：US17316777

申请日：2021-05-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byungjin Cho ,  Sungwon Shin ,  Euijoong Shin

IPC: H01L27/11597 ,  H01L29/51 ,  H01L27/1159 ,  H01L27/11592

Abstract: Semiconductor devices may include a stacked structure including interlayer insulating layers and gate electrodes alternately stacked in a vertical direction, a core region extending in the vertical direction in the stacked structure, a channel layer on a side surface of the core region and facing the gate electrodes and the interlayer insulating layers, a first dielectric layer, a data storage layer and a second dielectric layer, which are between the channel layer and the gate electrodes in order, and an anti-ferroelectric layer including a portion interposed between the first dielectric layer and a first gate electrode of the gate electrodes. The second dielectric layer may contact the channel layer. The anti-ferroelectric layer may be formed of an anti-ferroelectric material having a tetragonal phase.

公开(公告)号：US11744082B2

公开(公告)日：2023-08-29

申请号：US17316777

申请日：2021-05-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byungjin Cho ,  Sungwon Shin ,  Euijoong Shin

IPC: H10B51/20 ,  H01L29/51 ,  H10B51/30 ,  H10B51/40 ,  H10B43/40 ,  H10B43/20 ,  H10B43/30

CPC classification number: H10B51/20 ,  H01L29/516 ,  H10B43/20 ,  H10B43/30 ,  H10B43/40 ,  H10B51/30 ,  H10B51/40

Abstract: Semiconductor devices may include a stacked structure including interlayer insulating layers and gate electrodes alternately stacked in a vertical direction, a core region extending in the vertical direction in the stacked structure, a channel layer on a side surface of the core region and facing the gate electrodes and the interlayer insulating layers, a first dielectric layer, a data storage layer and a second dielectric layer, which are between the channel layer and the gate electrodes in order, and an anti-ferroelectric layer including a portion interposed between the first dielectric layer and a first gate electrode of the gate electrodes. The second dielectric layer may contact the channel layer. The anti-ferroelectric layer may be formed of an anti-ferroelectric material having a tetragonal phase.