公开(公告)号：US20220216227A1

公开(公告)日：2022-07-07

申请号：US17539523

申请日：2021-12-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangho RHA ,  Iksoo KIM ,  Jiwoon IM ,  Byungsun PARK ,  Seonkyu SHIN

IPC: H01L27/11556 ,  H01L27/11582 ,  G11C5/06 ,  G11C5/02 ,  H01L29/423

Abstract: A semiconductor device includes a memory cell structure on a substrate, and a dummy structure on a side of the memory cell structure. The memory cell structure includes a memory stack structure including interlayer insulating layers and gate electrodes alternately stacked on the substrate, channel structures penetrating through the memory stack structure and contacting the substrate, and first separation structures penetrating through the memory stack structure and extending in the first direction to separate the gate electrodes from each other in a second direction. The dummy structure includes dummy stack structures spaced apart from the memory stack structure and including first insulating layers and dummy gate electrodes alternately stacked, dummy channel structures penetrating through the dummy stack structures, and second separation structures penetrating through the dummy stack structures and extending in the second direction to separate the dummy gate electrodes from each other in the first direction.

公开(公告)号：US20220223524A1

公开(公告)日：2022-07-14

申请号：US17481609

申请日：2021-09-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Younseok CHOI ,  Byungsun PARK ,  Youngil LEE ,  Jaechul LEE ,  Jiwoon IM

IPC: H01L23/535 ,  H01L23/528 ,  H01L23/532 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582 ,  H01L27/11573 ,  H01L21/768

Abstract: A semiconductor device includes a lower memory stack disposed on a substrate and including lower gate electrodes and a lower staircase structure, an upper memory stack including upper gate electrodes and an upper staircase structure, a lower interlayer insulating layer doped with an impurity and covering the lower staircase structure, the lower interlayer insulating layer having a doping concentration gradually increasing toward the lower staircase structure, an upper interlayer insulating layer doped with an impurity and covering the upper staircase structure and the lower interlayer insulating layer, the upper interlayer insulating layer having a doping concentration gradually increasing toward the upper staircase structure and the lower interlayer insulating layer, lower contact plugs and upper contact plugs contacting the lower gate electrodes and the upper gate electrodes, respectively.