公开(公告)号：US20220406812A1

公开(公告)日：2022-12-22

申请号：US17689280

申请日：2022-03-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junsuk KIM ,  Donghoon KWON ,  Kiwoong KIM ,  Chungki MIN ,  Youngbeom PYON ,  Changsun HWANG

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L23/522 ,  H01L23/528

Abstract: A semiconductor device includes a substrate; a first stack structure including first gate electrodes on the substrate; and a second stack structure on the first stack structure; wherein the first stack structure includes a first lower staircase region, a second lower staircase region, and a third lower staircase region, wherein the second stack structure includes a first upper staircase region, a second upper staircase region, a third upper staircase region, and at least one through portion penetrating the second stack structure and on the first to third lower staircase regions, wherein the first lower staircase region has a same shape as a shape of the first upper staircase region, the second lower staircase region has a same shape as a shape of the second upper staircase region, and the third lower staircase region has a same shape as a shape of the third upper staircase region.

公开(公告)号：US20210375905A1

公开(公告)日：2021-12-02

申请号：US17140277

申请日：2021-01-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Changsun HWANG ,  Youngjin KWON ,  Gihwan KIM ,  Hansol SEOK ,  Dongseog EUN ,  Jongheun LIM

IPC: H01L27/11573 ,  H01L23/522 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582

Abstract: An integrated circuit device includes: a substrate having a cell region, a peripheral circuit region, and an interconnection region between the cell region and the peripheral circuit region; a first cell stack structure and a second cell stack structure on the first cell stack structure, each including a plurality of insulating layers and a plurality of word line structures alternately stacked on the substrate; and a dummy stack structure located at a same vertical level as the second cell stack structure, and including a plurality of dummy insulating layers and a plurality of dummy support layers alternately stacked in the peripheral circuit region.