公开(公告)号：US20220406812A1

公开(公告)日：2022-12-22

申请号：US17689280

申请日：2022-03-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junsuk KIM ,  Donghoon KWON ,  Kiwoong KIM ,  Chungki MIN ,  Youngbeom PYON ,  Changsun HWANG

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L23/522 ,  H01L23/528

Abstract: A semiconductor device includes a substrate; a first stack structure including first gate electrodes on the substrate; and a second stack structure on the first stack structure; wherein the first stack structure includes a first lower staircase region, a second lower staircase region, and a third lower staircase region, wherein the second stack structure includes a first upper staircase region, a second upper staircase region, a third upper staircase region, and at least one through portion penetrating the second stack structure and on the first to third lower staircase regions, wherein the first lower staircase region has a same shape as a shape of the first upper staircase region, the second lower staircase region has a same shape as a shape of the second upper staircase region, and the third lower staircase region has a same shape as a shape of the third upper staircase region.

公开(公告)号：US20190157279A1

公开(公告)日：2019-05-23

申请号：US16237913

申请日：2019-01-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngbeom PYON ,  Kichul PARK ,  Inkwon KIM ,  Ki Hoon JANG ,  Byoungho KWON ,  Sangkyun KIM ,  Boun YOON

IPC: H01L27/112 ,  H01L23/535 ,  H01L23/528 ,  H01L27/11582 ,  H01L27/11575 ,  H01L27/11573 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11551 ,  H01L27/11578

CPC classification number: H01L27/11286 ,  H01L21/02107 ,  H01L21/76801 ,  H01L21/76819 ,  H01L23/528 ,  H01L23/535 ,  H01L23/538 ,  H01L27/112 ,  H01L27/11551 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/11582

Abstract: A semiconductor device includes a substrate, a peripheral structure, a lower insulating layer, and a stack. The substrate includes a peripheral circuit region and a cell array region. The peripheral structure is on the peripheral circuit region. The lower insulating layer covers the peripheral circuit region and the cell array region and has a protruding portion protruding from a flat portion. The stack is on the lower insulating layer and the cell array region, and includes upper conductive patterns and insulating patterns which are alternately and repeatedly stacked.