公开(公告)号：US09419590B2

公开(公告)日：2016-08-16

申请号：US14267883

申请日：2014-05-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Matthew Berzins ,  Christina Wells

IPC: H03K3/012 ,  H03K3/037

CPC classification number: H03K3/012 ,  H03K3/037 ,  H03K3/0372

Abstract: Inventive aspects include integrated clock gating logic that can generate an internal glitch-free clock signal. Inventive aspects further include a toggle latch that is coupled to the integrated clock gating logic. The toggle latch can receive the internal clock signal from the integrated clock gating logic. The toggle latch can toggle and latch a data value responsive to the internal clock signal. The integrated clock gating logic can include a latch to latch a clock gating logic signal responsive to a clock signal. The clock gating logic signal can cause the internal clock signal to be quiescent when the input data to the flip-flop remains constant, thereby conserving power consumption.

Abstract translation: 发明方面包括可产生内部无毛刺时钟信号的集成时钟门控逻辑。 发明方面还包括耦合到集成时钟选通逻辑的触发锁存器。 触发锁存器可以从集成时钟门控逻辑接收内部时钟信号。 触发锁存器可以响应于内部时钟信号切换并锁存数据值。 集成时钟门控逻辑可以包括锁存器，以响应于时钟信号锁存时钟门控逻辑信号。 当触发器的输入数据保持不变时，时钟选通逻辑信号可能导致内部时钟信号静止，从而节省功耗。