公开(公告)号：US20220013476A1

公开(公告)日：2022-01-13

申请号：US17181617

申请日：2021-02-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： JI-YONG PARK ,  DUCKGYU KIM

IPC: H01L23/00 ,  H01L23/367 ,  H01L23/31 ,  H01L23/498

Abstract: Disclosed is a semiconductor package including a base film that has a first surface and a second surface opposite to the first surface, a plurality of input/output lines on the first surface of the base film, a semiconductor chip disposed on the first surface of the base film and connected to the input/output lines and including a central portion and end portions on opposite sides of the central portion, and a heat radiation pattern on the second surface of the base film The heat radiation pattern corresponds to the semiconductor chip and has a plurality of openings that correspond to the end portions of the semiconductor chip and that vertically overlap the end portions of the semiconductor chip.

公开(公告)号：US20250167054A1

公开(公告)日：2025-05-22

申请号：US18675860

申请日：2024-05-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DUCKGYU KIM

IPC: H01L21/66 ,  H01L23/544

Abstract: Disclosed are semiconductor chips and semiconductor packages including the same. The semiconductor chip comprises a substrate that includes a device region and an edge region, a conductive pad on the device region of the substrate, a residual test pattern on the edge region of the substrate, and a redistribution layer on the substrate and covering the conductive pad. The redistribution layer includes a first dielectric layer and a second dielectric layer. The residual test pattern includes a pattern cut part that has a lateral surface aligned with that of the substrate, and a pattern edge part between the pattern cut part and the conductive pad. The first dielectric layer entirely covers the pattern edge part and partially covers the pattern cut part. There is a step difference between sidewalls of the first and second dielectric layers such that the second dielectric layer does not cover the residual test pattern.

公开(公告)号：US20220068771A1

公开(公告)日：2022-03-03

申请号：US17230662

申请日：2021-04-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： MINKI KIM ,  DUCKGYU KIM ,  JAE-MIN JUNG ,  JEONG-KYU HA ,  SANG-UK HAN

IPC: H01L23/495 ,  H01L23/31 ,  H01L23/00 ,  H01L23/367

Abstract: Disclosed is a semiconductor package comprising a semiconductor chip, a first chip pad on a bottom surface of the semiconductor chip and adjacent to a first lateral surface in a first direction of the semiconductor chip, the first lateral surface separated from the first chip pad from a plan view in a first direction, and a first lead frame coupled to the first chip pad. The first lead frame includes a first segment on a bottom surface of the first chip pad and extending from the first chip pad in a second direction opposite to the first direction and away from the first lateral surface of the semiconductor chip, and a second segment which connects to a first end of the first segment and then extends along the first direction to extend beyond the first lateral surface of the semiconductor chip after passing one side of the first chip pad, when viewed in the plan view.

公开(公告)号：US20220173024A1

公开(公告)日：2022-06-02

申请号：US17675209

申请日：2022-02-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： GAYOUNG KIM ,  DUCKGYU KIM

IPC: H01L23/498 ,  H01L23/31

Abstract: A semiconductor package includes; a semiconductor chip, a conductive pattern electrically connected to the semiconductor chip, a pad electrically connected to the conductive pattern, and a connection member disposed on and electrically connected to the pad. The pad includes a central portion and a peripheral portion at least partially surrounding the central portion and separated from the peripheral portion by a gap, and the connection member contacts at least one of a side surface of the central portion and an inner side surface of the peripheral portion.

公开(公告)号：US20210151369A1

公开(公告)日：2021-05-20

申请号：US16905560

申请日：2020-06-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： GAYOUNG KIM ,  DUCKGYU KIM

IPC: H01L23/498

Abstract: A semiconductor package includes; a semiconductor chip, a conductive pattern electrically connected to the semiconductor chip, a pad electrically connected to the conductive pattern, and a connection member disposed on and electrically connected to the pad. The pad includes a central portion and a peripheral portion at least partially surrounding the central portion and separated from the peripheral portion by a gap, and the connection member contacts at least one of a side surface of the central portion and an inner side surface of the peripheral portion.