中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

7 records (took 0.015 seconds)

    SEMICONDUCTOR PACKAGE
    2.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20220068771A1

    公开(公告)日：2022-03-03

    申请号：US17230662

    申请日：2021-04-14

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： MINKI KIM ,  DUCKGYU KIM ,  JAE-MIN JUNG ,  JEONG-KYU HA ,  SANG-UK HAN

    IPC: H01L23/495 ,  H01L23/31 ,  H01L23/00 ,  H01L23/367

    Abstract: Disclosed is a semiconductor package comprising a semiconductor chip, a first chip pad on a bottom surface of the semiconductor chip and adjacent to a first lateral surface in a first direction of the semiconductor chip, the first lateral surface separated from the first chip pad from a plan view in a first direction, and a first lead frame coupled to the first chip pad. The first lead frame includes a first segment on a bottom surface of the first chip pad and extending from the first chip pad in a second direction opposite to the first direction and away from the first lateral surface of the semiconductor chip, and a second segment which connects to a first end of the first segment and then extends along the first direction to extend beyond the first lateral surface of the semiconductor chip after passing one side of the first chip pad, when viewed in the plan view.

    SEMICONDUCTOR PACKAGE
    3.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20240404970A1

    公开(公告)日：2024-12-05

    申请号：US18441578

    申请日：2024-02-14

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： MINKI KIM ,  RAEYOUNG KANG ,  JIHOON KIM ,  JINKYEONG SEOL ,  HYUEKJAE LEE

    IPC: H01L23/00 ,  H01L23/528 ,  H01L25/065

    Abstract: A semiconductor package includes a first die having signal and dummy regions, and a second die on the first die. The first die includes first dummy patterns arranged in a first direction on the dummy region, second dummy patterns on the dummy region and between the first dummy patterns, a first dielectric layer on the first and second dummy patterns, and first pads extending through the first dielectric layer and coupled to the first dummy patterns. The second die includes second pads on the dummy region, and third pads on the dummy region. On an interface between the first and second dies, the first pads are in contact with the second pads. The first dielectric layer is between the second dummy patterns and the third pads. The first dummy patterns are connected to a ground circuit or power circuit of the first die.

    SEMICONDUCTOR PACKAGE
    4.
    发明公开
    SEMICONDUCTOR PACKAGE 审中-公开

    公开(公告)号：US20240136311A1

    公开(公告)日：2024-04-25

    申请号：US18234529

    申请日：2023-08-15

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： GWANGJAE JEON ,  MINKI KIM ,  Hyungchul SHIN ,  WON IL LEE ,  HYUEKJAE LEE ,  Enbin JO

    IPC: H01L23/00 ,  H01L23/48

    CPC classification number: H01L24/06 ,  H01L23/481 ,  H01L24/05 ,  H01L24/08 ,  H01L2224/05557 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/06515 ,  H01L2224/08145

    Abstract: Disclosed is a semiconductor package comprising lower and upper structure. The lower structure includes a first semiconductor substrate, first through vias vertically penetrating the first semiconductor substrate, first signal pads connected to the first through vias, first dummy pads between the first signal pads and electrically separated from the first through vias, and a first dielectric layer surrounding the first signal pads and the first dummy pads. The upper structure includes a second semiconductor substrate, second signal pads and second dummy pads, and a second dielectric layer surrounding the second signal pads and the second dummy pads. The first signal pad is in contact with one of the second signal pads. The first dummy pad is in contact with one of the second dummy pads. A first interval between the first dummy pads is 0.5 to 1.5 times a second interval between the first signal pads.

    SEMICONDUCTOR PACKAGE
    5.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20250029942A1

    公开(公告)日：2025-01-23

    申请号：US18596286

    申请日：2024-03-05

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Raeyoung KANG ,  MINKI KIM ,  JIHOON KIM ,  JINKYEONG SEOL

    IPC: H01L23/00 ,  H01L23/48

    Abstract: A semiconductor package includes a lower structure and an upper structure on the lower structure. The lower structure includes a first substrate, a first through-electrode penetrating the first substrate in a first direction, a first pad connected to the first through-electrode, and a first protective layer surrounding the first pad. The upper structure includes a second substrate, a second through-electrode penetrating the second substrate in the first direction, a second pad connected to the second through-electrode, and a second protective layer surrounding the second pad. The second pad is offset from the first pad in a second direction crossing the first direction. The first pad has a first portion not overlapping the second pad. A first barrier pattern is disposed between the first portion and the second protective layer. A portion of the first barrier pattern is disposed between the first pad and the second pad.

    SEMICONDUCTOR PACKAGE
    6.
    发明公开
    SEMICONDUCTOR PACKAGE 审中-公开

    公开(公告)号：US20240234349A9

    公开(公告)日：2024-07-11

    申请号：US18234529

    申请日：2023-08-16

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： GWANGJAE JEON ,  MINKI KIM ,  Hyungchul SHIN ,  WON IL LEE ,  HYUEKJAE LEE ,  Enbin JO

    IPC: H01L23/00 ,  H01L23/48

    CPC classification number: H01L24/06 ,  H01L23/481 ,  H01L24/05 ,  H01L24/08 ,  H01L2224/05557 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/06515 ,  H01L2224/08145

    Abstract: Disclosed is a semiconductor package comprising lower and upper structure. The lower structure includes a first semiconductor substrate, first through vias vertically penetrating the first semiconductor substrate, first signal pads connected to the first through vias, first dummy pads between the first signal pads and electrically separated from the first through vias, and a first dielectric layer surrounding the first signal pads and the first dummy pads. The upper structure includes a second semiconductor substrate, second signal pads and second dummy pads, and a second dielectric layer surrounding the second signal pads and the second dummy pads. The first signal pad is in contact with one of the second signal pads. The first dummy pad is in contact with one of the second dummy pads. A first interval between the first dummy pads is 0.5 to 1.5 times a second interval between the first signal pads.

Patent Agency Ranking