公开(公告)号：US20230217658A1

公开(公告)日：2023-07-06

申请号：US17954968

申请日：2022-09-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Daehwan CHOI

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157

CPC classification number: H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157

Abstract: A method of manufacturing a semiconductor device includes forming a stacked structure by stacking gate layers and interlayer insulating layers alternately on a substrate; and forming a channel structure passing through the stacked structure in a vertical direction, wherein the forming a channel structure includes forming an opening by etching the stacked structure; forming a gate insulating layer covering a side surface of the opening; forming a variable resistive material layer on the gate insulating layer; changing an oxygen vacancy concentration in a region of the variable resistive material layer by performing a plasma treatment process or an annealing process on the variable resistive material layer; forming a core insulating pattern covering the variable resistive material layer and filling at least a portion of the opening; and forming a pad pattern on the core insulating pattern.

公开(公告)号：US20250142822A1

公开(公告)日：2025-05-01

申请号：US18653101

申请日：2024-05-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Daehwan CHOI

IPC: H10B43/27 ,  H01L25/065 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00

Abstract: A semiconductor device includes: a substrate including a cell array region and a contact region; a gate stacking structure including a plurality of interlayer insulation layers and a plurality of gate electrodes alternately stacked on the substrate; a channel structure penetrating the gate stacking structure in the cell array region; an upper insulation layer covering the gate stacking structure and the channel structure; and a plurality of gate contact parts penetrating the upper insulation layer and connected to the plurality of gate electrodes in the contact region, wherein at least a part of some of the plurality of gate contact parts penetrates at least one passing gate electrode among the plurality of gate electrodes and integrates with a connection gate electrode of the plurality of gate electrodes, and at least a part of an upper surface of the upper insulation layer has a concave shape protruding toward the substrate.

公开(公告)号：US20250008731A1

公开(公告)日：2025-01-02

申请号：US18392254

申请日：2023-12-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Daehwan CHOI ,  Hyuk KIM ,  Chanju PARK

IPC: H10B43/27

Abstract: A semiconductor device includes a cell array region and a contact region; a gate stack structure groups of gate electrodes; a channel structure extending through the gate stack structure in the cell array region; and gate contact portions connected to respective gate electrodes in the contact region. At least some of the gate contact portions extend through a through gate electrode connected to a connection gate electrode at a lower end portion. The gate contact portions include contact groups extending from a first side to a second side of the gate electrodes in an extending direction. Each of the electrode groups includes an upper group on a lower group. Each of the contact groups includes a first group connected to the upper group and a second group on the second side in the extending direction, and connected to the lower group, and a number of layers of the connection gate electrodes to which the gate contact portions are connected sequentially increases as a distance from a boundary between the first group and the second group increases in the first group and the second group.