公开(公告)号：US20200273780A1

公开(公告)日：2020-08-27

申请号：US16678620

申请日：2019-11-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwang Wuk Park ,  Sung Dong Cho ,  Eun Ji Kim ,  Hak Seung Lee ,  Dae Suk Lee ,  Dong Chan Lim ,  Sang Jun Park

IPC: H01L23/48 ,  H01L21/48

Abstract: A semiconductor device includes a substrate, an interlayer insulating layer on the substrate, a first etch stop layer on the substrate, a first through-silicon-via (TSV) configured to pass vertically through the substrate and the interlayer insulating layer, and a second TSV configured to pass vertically through the substrate, the interlayer insulating layer, and the first etch stop layer, wherein the second TSV has a width greater than that of the first TSV.

公开(公告)号：US11289402B2

公开(公告)日：2022-03-29

申请号：US16678620

申请日：2019-11-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwang Wuk Park ,  Sung Dong Cho ,  Eun Ji Kim ,  Hak Seung Lee ,  Dae Suk Lee ,  Dong Chan Lim ,  Sang Jun Park

IPC: H01L23/48 ,  H01L21/48

Abstract: A semiconductor device includes a substrate, an interlayer insulating layer on the substrate, a first etch stop layer on the substrate, a first through-silicon-via (TSV) configured to pass vertically through the substrate and the interlayer insulating layer, and a second TSV configured to pass vertically through the substrate, the interlayer insulating layer, and the first etch stop layer, wherein the second TSV has a width greater than that of the first TSV.

公开(公告)号：US11705386B2

公开(公告)日：2023-07-18

申请号：US17651456

申请日：2022-02-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwang Wuk Park ,  Sung Dong Cho ,  Eun Ji Kim ,  Hak Seung Lee ,  Dae Suk Lee ,  Dong Chan Lim ,  Sang Jun Park

IPC: H01L23/48 ,  H01L21/48

CPC classification number: H01L23/481 ,  H01L21/4814

Abstract: A semiconductor device includes a substrate, an interlayer insulating layer on the substrate, a first etch stop layer on the substrate, a first through-silicon-via (TSV) configured to pass vertically through the substrate and the interlayer insulating layer, and a second TSV configured to pass vertically through the substrate, the interlayer insulating layer, and the first etch stop layer, wherein the second TSV has a width greater than that of the first TSV.