公开(公告)号：US20240282705A1

公开(公告)日：2024-08-22

申请号：US18417847

申请日：2024-01-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong Ha SHIN ,  Jae Ick SON

IPC: H01L23/528 ,  H01L23/522 ,  H10B41/10 ,  H10B41/27 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/40

CPC classification number: H01L23/5283 ,  H01L23/5226 ,  H10B41/10 ,  H10B41/27 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/40

Abstract: A semiconductor memory device comprising a cell region on a cell substrate, and a peripheral circuit region on a peripheral circuit board connected to the cell region in a bonding manner is provided. Wherein the cell region comprises a plurality of gate electrodes sequentially stacked on a first side of the cell substrate, a first bypass cell contact plug extended in a vertical direction in an extended region connected to the first gate electrode, a normal cell contact plug extended in the vertical direction in the extended region and connected to the second gate electrode, a first metal wiring electrically connected to the first bypass cell contact plug and a second metal wiring on the first metal wiring and electrically connected to the first metal wiring, wherein the second metal wiring is connected with the fourth metal wiring through a first bypass path including a plurality of bonding metal pairs.