公开(公告)号：US20220084859A1

公开(公告)日：2022-03-17

申请号：US17536551

申请日：2021-11-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae Ick SON ,  Dae Seok BYEON ,  Bong Soon LIM

IPC: H01L21/67 ,  H01L21/66 ,  H01L23/00 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11573 ,  G11C8/14 ,  G11C7/18 ,  H01L25/18

Abstract: A semiconductor device includes a first semiconductor chip including bitlines, wordlines, common source line, first bonding pads, second bonding pads, third bonding pads and memory cells, the memory cells being electrically connected to the bitlines, the wordlines, and the common source line, the first bonding pads being electrically connected to the bitlines, the second bonding pads being electrically connected to the wordlines, and the third bonding pads being electrically connected to the common source line; a second semiconductor chip including fourth bonding pads, fifth bonding pads, sixth bonding pads and an input/output circuit, the fourth bonding pads being electrically connected to the first bonding pads, the fifth bonding pads being electrically connected to the second bonding pads, the sixth bonding pads being electrically connected to the third bonding pads and the input/output circuit being configured to write data to the memory cells via the fourth bonding pads and the fifth bonding pads; a sensing line extending along an edge portion of the first semiconductor chip, an edge portion of the second semiconductor chip, or the edge portion of the first semiconductor chip and the edge portion of the second semiconductor chip; and a detecting circuit in the second semiconductor chip, the detecting circuit being configured to detect defects from the first semiconductor chip, the second semiconductor chip, or both the first semiconductor chip and the second semiconductor chip using the sensing line.

公开(公告)号：US20240282705A1

公开(公告)日：2024-08-22

申请号：US18417847

申请日：2024-01-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong Ha SHIN ,  Jae Ick SON

IPC: H01L23/528 ,  H01L23/522 ,  H10B41/10 ,  H10B41/27 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/40

CPC classification number: H01L23/5283 ,  H01L23/5226 ,  H10B41/10 ,  H10B41/27 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/40

Abstract: A semiconductor memory device comprising a cell region on a cell substrate, and a peripheral circuit region on a peripheral circuit board connected to the cell region in a bonding manner is provided. Wherein the cell region comprises a plurality of gate electrodes sequentially stacked on a first side of the cell substrate, a first bypass cell contact plug extended in a vertical direction in an extended region connected to the first gate electrode, a normal cell contact plug extended in the vertical direction in the extended region and connected to the second gate electrode, a first metal wiring electrically connected to the first bypass cell contact plug and a second metal wiring on the first metal wiring and electrically connected to the first metal wiring, wherein the second metal wiring is connected with the fourth metal wiring through a first bypass path including a plurality of bonding metal pairs.

公开(公告)号：US20210090922A1

公开(公告)日：2021-03-25

申请号：US16995093

申请日：2020-08-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae Ick SON ,  Dae Seok BYEON ,  Bong Soon LIM

IPC: H01L21/67 ,  H01L25/18 ,  H01L21/66 ,  H01L23/00 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11573 ,  G11C8/14 ,  G11C7/18

Abstract: A semiconductor device includes a first semiconductor chip including bitlines, wordlines, common source line, first bonding pads, second bonding pads, third bonding pads and memory cells, the memory cells being electrically connected to the bitlines, the wordlines, and the common source line, the first bonding pads being electrically connected to the bitlines, the second bonding pads being electrically connected to the wordlines, and the third bonding pads being electrically connected to the common source line; a second semiconductor chip including fourth bonding pads, fifth bonding pads, sixth bonding pads and an input/output circuit, the fourth bonding pads being electrically connected to the first bonding pads, the fifth bonding pads being electrically connected to the second bonding pads, the sixth bonding pads being electrically connected to the third bonding pads and the input/output circuit being configured to write data to the memory cells via the fourth bonding pads and the fifth bonding pads; a sensing line extending along an edge portion of the first semiconductor chip, an edge portion of the second semiconductor chip, or the edge portion of the first semiconductor chip and the edge portion of the second semiconductor chip; and a detecting circuit in the second semiconductor chip, the detecting circuit being configured to detect defects from the first semiconductor chip, the second semiconductor chip, or both the first semiconductor chip and the second semiconductor chip using the sensing line.

公开(公告)号：US20210090663A1

公开(公告)日：2021-03-25

申请号：US16886053

申请日：2020-05-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae Ick SON ,  Dae Seok BYEON ,  Bong Soon LIM

IPC: G11C16/26 ,  G11C16/08 ,  G11C16/24 ,  G11C7/18 ,  G11C8/14 ,  H01L23/00

Abstract: A semiconductor device includes a first semiconductor chip, a second semiconductor chip, an input/output circuit, a sensing line, and a detecting circuit. The first semiconductor chip includes bitlines, wordlines, first bonding pads electrically connected to the bitlines, second bonding pads electrically connected to the wordlines, and memory cells electrically connected to the bitlines and the wordlines. The second semiconductor chip includes third bonding pads that are electrically connected to the first bonding pads and fourth bonding pads that are electrically connected to the second bonding pads. The input/output circuit writes data to the memory cells via the third bonding pads. The sensing line extends along edge portions of at least one of the first and second semiconductor chips. The detecting circuit is in the second semiconductor chip and can detect defects from at least one of the first and second semiconductor chips using the sensing line.