公开(公告)号：US20250098265A1

公开(公告)日：2025-03-20

申请号：US18636572

申请日：2024-04-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong Hoon Kwon

IPC: H01L29/417 ,  H01L23/528 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: A semiconductor device may include a first substrate, a lower pattern on a first side of the first substrate, a plurality of sheet patterns on the lower pattern and spaced apart from each other in a first direction, a gate electrode which surrounds portions the plurality of sheet patterns, a source/drain pattern which is on one side of the gate electrode and connected to the plurality of sheet patterns, a power rail which is on a second side of the first substrate, a via pattern which extends through the first substrate in the first direction, and is connected to both the power rail and the source/drain pattern, a first dummy pattern on the via pattern, a second substrate on the first dummy pattern, and a second dummy pattern on a third side of the second substrate that faces the first side of the first substrate.

公开(公告)号：US20250075103A1

公开(公告)日：2025-03-06

申请号：US18640617

申请日：2024-04-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： In Hyeong LEE ,  Dong Hoon Kwon

IPC: C09G1/02 ,  H01L21/02

Abstract: A slurry solution includes an abrasive including a first frame portion including an oxide and having a spherical shape, a plurality of pores in the abrasive, and a plurality of first abrasive elements at least partially filling the plurality of pores, where the plurality of first abrasive elements include Ce(OH)4.

公开(公告)号：US20240395712A1

公开(公告)日：2024-11-28

申请号：US18530763

申请日：2023-12-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong Hoon Kwon ,  Il Young Yoon

IPC: H01L23/528 ,  H01L21/8238 ,  H01L23/48 ,  H01L27/092

Abstract: A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a substrate including a frontside on which an active pattern is formed and a backside opposite the frontside, an electronic element on an active region in which the active pattern is formed, a frontside interconnection structure, in which a power line connected to the electronic element is disposed, on the frontside of the substrate, a backside interconnection structure, which includes a backside line connected to the electronic element, on the backside of the substrate, a through via connecting the power line with the backside line by passing through the substrate, and a dummy mold structure on the frontside interconnection structure, having a first cross-sectional thickness greater than a second cross-sectional thickness of the frontside interconnection structure.