公开(公告)号：US20210233879A1

公开(公告)日：2021-07-29

申请号：US17229023

申请日：2021-04-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju-il CHOI ,  Kwangjin MOON ,  Sujeong PARK ,  JuBin SEO ,  Jin Ho AN ,  Dong-chan LIM ,  Atsushi FUJISAKI

IPC: H01L23/00

Abstract: Disclosed is a semiconductor device including a conductive pattern on a substrate, a passivation layer on the substrate and including an opening that partially exposes the conductive pattern, and a pad structure in the opening of the passivation layer and connected to the conductive pattern. The pad structure includes a first metal layer that fills the opening of the passivation layer and has a width greater than that of the opening, and a second metal layer on the first metal layer. The first metal layer has a first thickness at an outer wall of the first metal layer, a second thickness on a top surface of the passivation layer, and a third thickness on a top surface of the conductive pattern. The second thickness is greater than the first thickness, and the third thickness is greater than the second thickness.

公开(公告)号：US20200027784A1

公开(公告)日：2020-01-23

申请号：US16242122

申请日：2019-01-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Su-jeong PARK ,  Dong-chan LIM ,  Kwang-jin MOON ,  Ju-bin SEO ,  Ju-ll CHOI ,  Atsushi FUJISAKI

IPC: H01L21/768

Abstract: An integrated circuit device includes a substrate, a landing pad on the substrate, and a through-via structure passing through the substrate and connected to the landing pad. The through-via structure may include a conductive plug, a first conductive barrier layer covering a sidewall and a lower surface of the conductive plug, and a second conductive barrier layer covering a sidewall of the first conductive barrier layer.