公开(公告)号：US20210233879A1

公开(公告)日：2021-07-29

申请号：US17229023

申请日：2021-04-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju-il CHOI ,  Kwangjin MOON ,  Sujeong PARK ,  JuBin SEO ,  Jin Ho AN ,  Dong-chan LIM ,  Atsushi FUJISAKI

IPC: H01L23/00

Abstract: Disclosed is a semiconductor device including a conductive pattern on a substrate, a passivation layer on the substrate and including an opening that partially exposes the conductive pattern, and a pad structure in the opening of the passivation layer and connected to the conductive pattern. The pad structure includes a first metal layer that fills the opening of the passivation layer and has a width greater than that of the opening, and a second metal layer on the first metal layer. The first metal layer has a first thickness at an outer wall of the first metal layer, a second thickness on a top surface of the passivation layer, and a third thickness on a top surface of the conductive pattern. The second thickness is greater than the first thickness, and the third thickness is greater than the second thickness.

公开(公告)号：US20190013260A1

公开(公告)日：2019-01-10

申请号：US16131182

申请日：2018-09-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju-il CHOI ,  Kun-sang PARK ,  Son-kwan HWANG ,  Ji-soon PARK ,  Byung-lyul PARK

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/31 ,  H01L25/065 ,  H01L23/532

Abstract: An integrated circuit (IC) device includes a semiconductor substrate having a via hole extending through at least a part thereof, a conductive structure in the via hole, a conductive barrier layer adjacent the conductive structure; and a via insulating layer interposed between the semiconductor substrate and the conductive barrier layer. The conductive barrier layer may include an outer portion oxidized between the conductive barrier layer and the via insulating layer, and the oxidized outer portion of the conductive barrier layer may substantially surrounds the remaining portion of the conductive barrier layer.

公开(公告)号：US20230187393A1

公开(公告)日：2023-06-15

申请号：US18168038

申请日：2023-02-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju-il CHOI ,  Kwangjin Moon ,  Sujeong Park ,  JuBin Seo ,  Jin Ho An ,  Dong-chan Lim ,  Atsushi Fujisaki

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L24/06 ,  H01L24/16 ,  H01L24/17 ,  H01L24/03 ,  H01L2224/17181 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/03825 ,  H01L2224/03914 ,  H01L2224/05017 ,  H01L2224/05018 ,  H01L2224/05019 ,  H01L2224/05082 ,  H01L2224/05015 ,  H01L2224/05027 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05644 ,  H01L2224/05564 ,  H01L2224/05573 ,  H01L2224/06182 ,  H01L2224/06136 ,  H01L2224/02372 ,  H01L2224/16145 ,  H01L2224/16227

Abstract: Disclosed is a semiconductor device including a conductive pattern on a substrate, a passivation layer on the substrate and including an opening that partially exposes the conductive pattern, and a pad structure in the opening of the passivation layer and connected to the conductive pattern. The pad structure includes a first metal layer that fills the opening of the passivation layer and has a width greater than that of the opening, and a second metal layer on the first metal layer. The first metal layer has a first thickness at an outer wall of the first metal layer, a second thickness on a top surface of the passivation layer, and a third thickness on a top surface of the conductive pattern. The second thickness is greater than the first thickness, and the third thickness is greater than the second thickness.