公开(公告)号：US20250077437A1

公开(公告)日：2025-03-06

申请号：US18762201

申请日：2024-07-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Moongyung Kim ,  Youngsik Eom ,  Donghyeon Ham

IPC: G06F12/0873 ,  G06F12/0891

Abstract: The present disclosure relates to an electronic device, a memory device, and an operating method of the memory device. An example memory device includes a first bank, a second bank, and a cache controller. The cache controller is configured to set a hash function based on a power control signal that comprises instructions to stop supplying power to the first bank, and to map the first address and the second bank based on the hash function and a first transaction provided by a master after the power control signal is input.

公开(公告)号：US10592454B2

公开(公告)日：2020-03-17

申请号：US16034470

申请日：2018-07-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Youl Kim ,  Chih Jen Lin ,  Jinook Song ,  Sungjae Lee ,  Hyun-ki Koo ,  Donghyeon Ham

IPC: G06F13/40 ,  G06F13/16 ,  G06T1/20

Abstract: A system-on-chip (SoC) to perform a deadlock control on a processor of the SoC, the SoC including the processor including a plurality of central processing unit (CPU) cores, a first bus connected to the processor, a graphic processing unit (GPU) connected to the first bus, a memory controller connected to the first bus, a second bus connected to the processor, an isolation cell including a logic circuit configured to retain a signal value input to the processor according to an isolation signal, and a deadlock controller connected to the first bus and the second bus. The deadlock controller is configured to isolate the processor, which is in a deadlock state, from the first bus by applying the isolation signal on the isolation cell, and to extract, via the second bus, state information of the isolated processor in the deadlock state.

公开(公告)号：US20250077427A1

公开(公告)日：2025-03-06

申请号：US18802266

申请日：2024-08-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Moongyung Kim ,  Youngsik Eom ,  Donghyeon Ham

IPC: G06F12/0806 ,  G06F12/0891

Abstract: The present disclosure relates to electronic devices, memory devices, and memory device operating methods. An example memory device includes a first bank, a second bank, a cache controller, and a way selector. The first bank includes a first way group configured to receive power and to store a first cache line corresponding to a first address. The second bank includes a second way group configured to receive power and to store a second cache line corresponding to a second address. The cache controller is configured to output a second target indicating the second bank based on a power control signal indicating to stop supplying the power to the first bank and the first address. The way selector is configured to transmit the first address to the second bank based on the first address, the power control signal, and the second target.

公开(公告)号：US10025741B2

公开(公告)日：2018-07-17

申请号：US14995179

申请日：2016-01-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Youl Kim ,  Chih Jen Lin ,  Jinook Song ,  Sungjae Lee ,  Hyun-ki Koo ,  Donghyeon Ham

IPC: G06F13/00 ,  G06F13/36 ,  G06F13/40 ,  G06F13/16 ,  G06T1/20

Abstract: A system-on-chip (SoC) to perform a deadlock control on a processor of the SoC, the SoC including the processor including a plurality of central processing unit (CPU) cores, a first bus connected to the processor, a graphic processing unit (GPU) connected to the first bus, a memory controller connected to the first bus, a second bus connected to the processor, an isolation cell including a logic circuit configured to retain a signal value input to the processor according to an isolation signal, and a deadlock controller connected to the first bus and the second bus. The deadlock controller is configured to isolate the processor, which is in a deadlock state, from the first bus by applying the isolation signal on the isolation cell, and to extract, via the second bus, state information of the isolated processor in the deadlock state.