公开(公告)号：US12248868B2

公开(公告)日：2025-03-11

申请号：US17376516

申请日：2021-07-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun-Woo Jang ,  Jinook Song ,  Sehwan Lee

IPC: G06N3/06 ,  G06N3/04 ,  G06N3/063

Abstract: A neural processing device includes a first memory configured to store universal data, a second memory distinguished from the first memory and having a capacity less than that of the first memory, a bandwidth control path configured to reconfigure a memory bandwidth for memory clients to use one of the first memory and the second memory based on a control signal, and a control logic configured to calculate a target capacity for data of a target client of the memory clients determined based on a layer configuration of an artificial neural network, and generate the control signal to store the data of the target client in the second memory based on a result of comparing the target capacity and the capacity of the second memory.

公开(公告)号：US10025741B2

公开(公告)日：2018-07-17

申请号：US14995179

申请日：2016-01-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Youl Kim ,  Chih Jen Lin ,  Jinook Song ,  Sungjae Lee ,  Hyun-ki Koo ,  Donghyeon Ham

IPC: G06F13/00 ,  G06F13/36 ,  G06F13/40 ,  G06F13/16 ,  G06T1/20

Abstract: A system-on-chip (SoC) to perform a deadlock control on a processor of the SoC, the SoC including the processor including a plurality of central processing unit (CPU) cores, a first bus connected to the processor, a graphic processing unit (GPU) connected to the first bus, a memory controller connected to the first bus, a second bus connected to the processor, an isolation cell including a logic circuit configured to retain a signal value input to the processor according to an isolation signal, and a deadlock controller connected to the first bus and the second bus. The deadlock controller is configured to isolate the processor, which is in a deadlock state, from the first bus by applying the isolation signal on the isolation cell, and to extract, via the second bus, state information of the isolated processor in the deadlock state.

公开(公告)号：US12175208B2

公开(公告)日：2024-12-24

申请号：US16989391

申请日：2020-08-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinook Song ,  Daekyeung Kim ,  Junseok Park ,  Joonho Song ,  Sehwan Lee ,  Junwoo Jang ,  Yunkyo Cho

IPC: G06F7/544 ,  G06N3/063

Abstract: An arithmetic apparatus includes a first operand holding circuit configured to output a first operand according to a clock signal, generate an indicator signal based on bit values of high-order bit data including a most significant bit of the first operand, and gate the clock signal based on the indicator signal, the clock signal being applied to a flip-flop latching the high-order bit data of the first operand; a second operand holding circuit configured to output a second operand according to the clock signal; and an arithmetic circuit configured to perform data gating on the high-order bit data of the first operand based on the indicator signal and output an operation result by performing an operation using a modified first operand resulting from the data gating and the second operand.

公开(公告)号：US10592454B2

公开(公告)日：2020-03-17

申请号：US16034470

申请日：2018-07-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Youl Kim ,  Chih Jen Lin ,  Jinook Song ,  Sungjae Lee ,  Hyun-ki Koo ,  Donghyeon Ham

IPC: G06F13/40 ,  G06F13/16 ,  G06T1/20

Abstract: A system-on-chip (SoC) to perform a deadlock control on a processor of the SoC, the SoC including the processor including a plurality of central processing unit (CPU) cores, a first bus connected to the processor, a graphic processing unit (GPU) connected to the first bus, a memory controller connected to the first bus, a second bus connected to the processor, an isolation cell including a logic circuit configured to retain a signal value input to the processor according to an isolation signal, and a deadlock controller connected to the first bus and the second bus. The deadlock controller is configured to isolate the processor, which is in a deadlock state, from the first bus by applying the isolation signal on the isolation cell, and to extract, via the second bus, state information of the isolated processor in the deadlock state.