MEMORY DEVICE AND REFRESH METHOD THEREOF

    公开(公告)号:US20250156544A1

    公开(公告)日:2025-05-15

    申请号:US18662995

    申请日:2024-05-13

    Abstract: A memory device may include an attack row selector configured to receive an activation signal at a first time point, and generate an update signal based on an accumulation value, an attack row register configured to receive an activation row address corresponding to the activation signal, and determine an attack row address based on the update signal and the activation row address, and a victim row determiner configured to determine a victim row address based on the attack row address. The accumulation value may be the number of activation signals received from a second time point before the first time point to the first time point.

    Memory device and refresh method thereof

    公开(公告)号:US12236996B2

    公开(公告)日:2025-02-25

    申请号:US18197084

    申请日:2023-05-14

    Abstract: A memory device may include counters respectively corresponding to rows and each configured to count a number of accesses to a corresponding row, a refresh control circuit, a queue, and first flags respectively corresponding to the rows. The refresh control circuit may change a second flag set in a refresh period every refresh period, and determine whether to put an incoming row address into the queue based on a count value of a counter corresponding to a target row indicated by the incoming row address among the counters, a first flag value of a first flag corresponding to the target row among the first flags, and a second flag value of the second flag set in a current refresh period.

Patent Agency Ranking