公开(公告)号：US12288578B2

公开(公告)日：2025-04-29

申请号：US17864736

申请日：2022-07-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunghye Cho ,  Kijun Lee ,  Myungkyu Lee ,  Eunae Lee ,  Byeonggyu Park ,  Yeonggeol Song

IPC: G11C11/406 ,  G11C11/4093

Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory cell rows, a row hammer management circuit, and a refresh control circuit. The row hammer management circuit captures row addresses accompanied by first active commands randomly selected from active commands, each of which has a first selection probability that is uniform, from an external memory controller during a reference time interval, and selects at least one row address from among the captured row addresses as a hammer address a number of times proportional to access counts of an active command corresponding to the at least one row address during the reference time interval. The refresh control circuit receives the hammer address and performs a hammer refresh operation on one or more victim memory cell rows which are physically adjacent to a memory cell row corresponding to the hammer address.

公开(公告)号：US20240385925A1

公开(公告)日：2024-11-21

申请号：US18543737

申请日：2023-12-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myungkyu Lee ,  Seongmuk Kang ,  Daehyun Kim ,  Jiho Kim ,  Kyomin Sohn ,  Kijun Lee ,  Sunghye Cho

IPC: G06F11/10 ,  G06F11/00 ,  G06F11/07

Abstract: A memory system includes a plurality of volatile memory devices and a memory controller. The memory controller includes a plurality of volatile memory devices; and a memory controller configured to control the plurality of volatile memory devices, wherein the memory controller includes: a host interface configured to communicate with a host device based on a Compute eXpress Link (CXL) communication protocol; an error correction level (ECL) manager configured to receive cache line data from the host device through the host interface, and output an error correction code (ECC) control signal indicating one of a first correction level and a second correction level being error correction levels based on cell reliability information and data reliability request information which are associated with the cache line data; and an ECC engine configured to, based on the ECC control signal indicating the first correction level, generate first parity symbols associated with the cache line data, and based on the ECC control signal indicating the second correction level, generate additional parity symbols.

公开(公告)号：US20230178168A1

公开(公告)日：2023-06-08

申请号：US18164100

申请日：2023-02-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunghye Cho ,  Kiheung Kim ,  Sungrae Kim ,  Junhyung Kim ,  Kijun Lee ,  Myungkyu Lee ,  Changyong Lee ,  Sanguhn Cha

IPC: G11C29/42 ,  G11C29/44 ,  G11C11/408 ,  G11C11/4091

CPC classification number: G11C29/42 ,  G11C29/4401 ,  G11C11/4087 ,  G11C11/4091 ,  G11C2029/1204

Abstract: A memory system includes a memory module having a plurality of memory devices therein. A memory controller is configured to transmit commands and addresses to the memory module in synchronization with a clock, input/output data to and from the memory module in synchronization with a data transfer clock, and perform system error correction operations on data read from the memory module. The plurality of memory devices perform on-die error correction operations, which are different from each other according to a physical location of the stored read data.

公开(公告)号：US20230147227A1

公开(公告)日：2023-05-11

申请号：US17814964

申请日：2022-07-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Suhun Lim ,  Kijun Lee ,  Myungkyu Lee ,  Eunchul Kwon ,  Hoyoun Kim ,  Jongmin Lee

IPC: G06F11/10 ,  G06F11/07 ,  H03M13/15 ,  G06F17/16

CPC classification number: G06F11/1068 ,  G06F11/0772 ,  G06F11/076 ,  H03M13/1575 ,  G06F17/16

Abstract: A memory controller includes an error correction code (ECC) engine and an error managing circuit. The ECC engine is configured to, during a read operation, perform an ECC decoding on a read codeword set to generate a first and second syndrome associated with a correctable error in a user data set included in the read codeword set, correct the correctable error based on the first syndrome and the second syndrome, and provide the second syndrome to the error managing circuit. The error managing circuit is configured to accumulate second syndromes associated with a plurality of correctable errors and obtained through a plurality of read operations as a plurality of second syndromes, store the plurality of second syndromes, compare the plurality of second syndromes with an error pattern set, and predict an occurrence of an uncorrectable error associated with the correctable error in a memory region based on the comparison.

公开(公告)号：US20230119555A1

公开(公告)日：2023-04-20

申请号：US17736154

申请日：2022-05-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungrae Kim ,  Sunghye Cho ,  Yeonggeol Song ,  Kijun Lee ,  Myungkyu Lee

IPC: G06F11/10 ,  G06F11/07 ,  H03M13/11

Abstract: A semiconductor memory device includes a memory cell array, an on-die error correction code (ECC) engine, and a control logic circuit. The on-die ECC engine, based on an ECC, in a write operation, performs an ECC encoding on main data to generate first parity data, selectively replaces a portion of the first parity data with a poison flag to generate second parity data based on a poison mode signal, provides the main data to a normal cell region in a target page of the memory cell array, and provides the first parity data to a parity cell region in the target page or provides the poison flag and the second parity data to the parity cell region. The control logic circuit controls the on-die ECC engine and generates the poison mode signal, based on a command and an address from a memory controller.

公开(公告)号：US11614869B2

公开(公告)日：2023-03-28

申请号：US17226606

申请日：2021-04-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hoyoun Kim ,  Kijun Lee ,  Myungkyu Lee

IPC: G06F3/06

Abstract: A memory system is provided. The memory system includes at least one memory device, and a controller configured to control the at least one memory device, wherein the controller includes: an error correction circuit configured to correct an error in data read from the at least one memory device, a codeword error counter configured to obtain a syndrome of a current codeword error based on a codeword error occurring in the error correction circuit, and to obtain a weighted codeword error count value by comparing the obtained syndrome with a previous syndrome, and an alert device configured to generate a warning signal for preventing an uncorrectable error of the at least one memory device according to the weighted codeword error count value.

公开(公告)号：US20220405165A1

公开(公告)日：2022-12-22

申请号：US17535762

申请日：2021-11-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yeonggeol Song ,  Sungrae Kim ,  Kijun Lee ,  Sunggi Ahn ,  Yesin Ryu ,  Sukhan Lee

IPC: G06F11/10 ,  G11C29/04

Abstract: A semiconductor memory device includes a buffer die and a plurality of memory dies. Each of the memory dies includes a memory cell array, an error correction code (ECC) engine and a test circuit. The memory cell array includes a plurality of memory cell rows, each including a plurality of volatile memory cells. The test circuit, in a test mode, generates a test syndrome and an expected decoding status flag indicating error status of the test syndrome, receives test parity data generated by the ECC engine based on the test syndrome and a decoding status flag indicating error status of the test parity data, and determines whether the ECC engine has a defect based on comparison of the test syndrome and the test parity data and a comparison of the expected decoding status flag and the decoding status flag.

公开(公告)号：US20210311821A1

公开(公告)日：2021-10-07

申请号：US17088900

申请日：2020-11-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yesin Ryu ,  Namsung KIM ,  Sanguhn CHA ,  Jaeyoun Youn ,  Kijun Lee

IPC: G06F11/10 ,  H01L25/065

Abstract: A semiconductor memory device including: a buffer die; memory dies stacked on the buffer die; and TSVs, at least one of the memory dies includes: a memory cell array; an error correction code (ECC) engine; an error information register; and a control logic circuit configured to control the ECC engine to perform a read-modify-write operation, wherein the control logic circuit is configured to: record, in the error information register, a first address associated with a first codeword based on the an generation signal and a first syndrome obtained by an ECC decoding; and determine an error attribute of the first codeword based on a change of the first syndrome, recorded in the error information register, based on a plurality of read-modify-write operations.

公开(公告)号：US11037646B2

公开(公告)日：2021-06-15

申请号：US16357431

申请日：2019-03-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minuk Kim ,  Bohwan Jun ,  Hong Rak Son ,  Dong-Min Shin ,  Kijun Lee

IPC: G11C29/42 ,  G06F11/10 ,  G06F3/06

Abstract: An operating method of a memory controller that individually controls a plurality of memory units includes reading respective segments from the plurality of memory units based on a plurality of control signals; generating an output codeword based on the segments; performing error correction decoding on the output codeword; when a result of the error correction decoding indicates success, updating at least one of a plurality of accumulated error pattern information respectively corresponding to the plurality of memory units based on the result of the error correction decoding; and when the result of the error correction decoding indicates failure, regulating at least one of the plurality of control signals based on at least one of the plurality of accumulated error pattern information.

公开(公告)号：US12236991B1

公开(公告)日：2025-02-25

申请号：US18188256

申请日：2023-03-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eunae Lee ,  Sunghye Cho ,  Kijun Lee ,  Junjin Kong ,  Yeonggeol Song

IPC: G11C11/406 ,  G06F12/06 ,  G11C11/408

Abstract: A memory device includes a memory cell array, an address manager and a refresh controller. The memory cell array includes a plurality of memory cells coupled to a plurality of word-lines. The address manager samples access addresses provided from a memory controller to generate sampling addresses and determines a capture address from among the access addresses, based on a time interval between refresh commands from the memory controller. The refresh controller refreshes target memory cells from among the plurality of memory cells based on one of a maximum access address from among the sampling address and the captured address.