公开(公告)号：US20190304993A1

公开(公告)日：2019-10-03

申请号：US16149848

申请日：2018-10-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taehee LEE ,  Hyunwook Kim ,  Eun-jung Yang

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157

Abstract: Disclosed are three-dimensional semiconductor memory devices including an electrode structure including gate electrodes stacked in a first direction, a lower pattern group including lower vertical patterns that are in a lower portion of the electrode structure and are connected to the substrate, and an upper pattern group including upper vertical patterns that are in an upper portion of the electrode structure. The upper vertical patterns may be connected to the lower vertical patterns, respectively. The devices may also include two common source plugs spaced apart from each other in a second direction. The electrode structure may be between the two common source plugs. An upper portion of the lower pattern group has a first width in the second direction, an upper portion of the upper pattern group has a second width in the second direction, and the first width may be greater than the second width.

公开(公告)号：US11659712B2

公开(公告)日：2023-05-23

申请号：US17712225

申请日：2022-04-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taehee Lee ,  Hyunwook Kim ,  Eun-jung Yang

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11565

CPC classification number: H01L27/11582 ,  H01L27/1157 ,  H01L27/11565

Abstract: Disclosed are three-dimensional semiconductor memory devices including an electrode structure including gate electrodes stacked in a first direction, a lower pattern group including lower vertical patterns that are in a lower portion of the electrode structure and are connected to the substrate, and an upper pattern group including upper vertical patterns that are in an upper portion of the electrode structure. The upper vertical patterns may be connected to the lower vertical patterns, respectively. The devices may also include two common source plugs spaced apart from each other in a second direction. The electrode structure may be between the two common source plugs. An upper portion of the lower pattern group has a first width in the second direction, an upper portion of the upper pattern group has a second width in the second direction, and the first width may be greater than the second width.

公开(公告)号：US10553610B2

公开(公告)日：2020-02-04

申请号：US16149848

申请日：2018-10-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taehee Lee ,  Hyunwook Kim ,  Eun-jung Yang

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11565

Abstract: Disclosed are three-dimensional semiconductor memory devices including an electrode structure including gate electrodes stacked in a first direction, a lower pattern group including lower vertical patterns that are in a lower portion of the electrode structure and are connected to the substrate, and an upper pattern group including upper vertical patterns that are in an upper portion of the electrode structure. The upper vertical patterns may be connected to the lower vertical patterns, respectively. The devices may also include two common source plugs spaced apart from each other in a second direction. The electrode structure may be between the two common source plugs. An upper portion of the lower pattern group has a first width in the second direction, an upper portion of the upper pattern group has a second width in the second direction, and the first width may be greater than the second width.