SEMICONDUCTOR DEVICE INCLUDING PARTIALLY ENLARGED CHANNEL HOLE

    公开(公告)号:US20200020713A1

    公开(公告)日:2020-01-16

    申请号:US16203790

    申请日:2018-11-29

    Abstract: A semiconductor device includes a lower stack structure on a substrate, an upper stack structure on the lower stack structure, and a channel structure in a channel hole formed through the upper stack structure and the lower stack structure. The channel hole includes a lower channel hole in the lower stack structure, an upper channel hole in the upper stack structure, and a partial extension portion adjacent to an interface between the lower stack structure and the upper stack structure. The partial extension portion is in fluid communication with the lower channel hole and the upper channel hole. A lateral width of the partial extension portion may be greater than a lateral width of the upper channel hole adjacent to the partial extension portion and greater than a lateral width of the upper channel hole adjacent to the partial extension portion.

    SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES

    公开(公告)号:US20230123932A1

    公开(公告)日:2023-04-20

    申请号:US17959365

    申请日:2022-10-04

    Abstract: A method of manufacturing a semiconductor device includes forming a molded structure of stacked and alternating interlayer insulating layers and sacrificial layers on a lower structure, forming a hole through the molded structure, forming recess regions in the sacrificial layers of the molded structure, respectively, by removing a portion of the sacrificial layers, exposed through the hole, from side surfaces of the sacrificial layers, sequentially forming a preliminary blocking pattern and a charge storage pattern in each of the recess regions, sequentially forming a tunneling layer and a channel layer in the hole, forming trenches penetrating through the molded structure, such that the trenches extend in a line shape, removing the sacrificial layers exposed by the trenches, such that the preliminary blocking pattern is exposed, and oxidizing the preliminary blocking pattern, after removing the sacrificial layers, such that a blocking pattern is formed.

    BATCH TYPE SUBSTRATE PROCESSING APPARATUS AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE USING THE SAME

    公开(公告)号:US20230054580A1

    公开(公告)日:2023-02-23

    申请号:US17826901

    申请日:2022-05-27

    Abstract: A substrate processing apparatus and a method of manufacturing a semiconductor device are provided. The substrate processing apparatus includes a processing chamber; a boat configured to stack substrates; a gas nozzle including a nozzle region and a fastening region; a gas inlet including an insert portion; and an adapter coupling the gas inlet and the gas nozzle. The fastening region includes a first lower region; and a second lower region having a protruding portion protruding outwardly from an outer side surface of the first lower region. The adapter includes a lower pedestal; a lower fastening portion on the lower pedestal and contacting at least a lower surface of the protruding portion; a gasket between a portion of the lower pedestal and a portion of the lower fastening portion; an upper fastening portion contacting at least an upper surface of the protruding portion; a hole passing through the lower pedestal, the lower fastening portion, the protruding portion, and the upper fastening portion; and a fastening unit coupling the lower pedestal, the lower fastening portion, the protruding portion, and the upper fastening portion through the hole.

    SEMICONDUCTOR DEVICE INCLUDING PARTIALLY ENLARGED CHANNEL HOLE

    公开(公告)号:US20200350332A1

    公开(公告)日:2020-11-05

    申请号:US16930711

    申请日:2020-07-16

    Abstract: A semiconductor device includes a lower stack structure on a substrate, an upper stack structure on the lower stack structure, and a channel structure in a channel hole formed through the upper stack structure and the lower stack structure. The channel hole includes a lower channel hole in the lower stack structure, an upper channel hole in the upper stack structure, and a partial extension portion adjacent to an interface between the lower stack structure and the upper stack structure. The partial extension portion is in fluid communication with the lower channel hole and the upper channel hole. A lateral width of the partial extension portion may be greater than a lateral width of the upper channel hole adjacent to the partial extension portion and greater than a lateral width of the upper channel hole adjacent to the partial extension portion.

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