公开(公告)号：US20200020713A1

公开(公告)日：2020-01-16

申请号：US16203790

申请日：2018-11-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunyeoung CHOI ,  Hyung Joon Kim ,  Bio Kim ,  Yujin Kim ,  Junggeun Jee

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L23/532

Abstract: A semiconductor device includes a lower stack structure on a substrate, an upper stack structure on the lower stack structure, and a channel structure in a channel hole formed through the upper stack structure and the lower stack structure. The channel hole includes a lower channel hole in the lower stack structure, an upper channel hole in the upper stack structure, and a partial extension portion adjacent to an interface between the lower stack structure and the upper stack structure. The partial extension portion is in fluid communication with the lower channel hole and the upper channel hole. A lateral width of the partial extension portion may be greater than a lateral width of the upper channel hole adjacent to the partial extension portion and greater than a lateral width of the upper channel hole adjacent to the partial extension portion.

公开(公告)号：US10411034B2

公开(公告)日：2019-09-10

申请号：US16001975

申请日：2018-06-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woo Jin Jang ,  Young Jin Noh ,  Jun Kyu Yang ,  Bio Kim ,  Kyong Won An

IPC: H01L27/11582 ,  H01L21/28 ,  H01L29/06 ,  H01L29/10 ,  H01L29/51 ,  H01L23/528 ,  H01L21/311 ,  H01L21/3115 ,  H01L21/02 ,  H01L23/522 ,  H01L27/11565

Abstract: An integrated circuit memory device includes a vertical stack structure containing an interlayer insulating layer and a gate electrode, on a substrate. A blocking dielectric region is provided on a sidewall of an opening in the stack structure. A lateral impurity region is provided, which extends between the blocking dielectric region and the interlayer insulating layer and between the blocking dielectric region and the gate electrode. A lower impurity region is also provided, which extends between the blocking dielectric region and the substrate.

公开(公告)号：US11329063B2

公开(公告)日：2022-05-10

申请号：US16848035

申请日：2020-04-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bio Kim ,  Yujin Kim ,  Philouk Nam ,  Youngseon Son ,  Kyongwon An ,  Jumi Yun ,  Woojin Jang

IPC: H01L27/11578 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L29/423 ,  H01L21/02 ,  H01L27/1157 ,  H01L21/28

Abstract: A vertical memory device includes a channel extending in a vertical direction on a substrate, a charge storage structure on an outer sidewall of the channel and including a tunnel insulation pattern, a charge trapping pattern, and a first blocking pattern sequentially stacked in a horizontal direction, and gate electrodes spaced apart from each other in the vertical direction, each of which surrounds the charge storage structure. The charge storage structure includes charge trapping patterns, each of which faces one of the gate electrodes in the horizontal direction. A length in the vertical direction of an inner sidewall of each of the charge trapping patterns facing the tunnel insulation pattern is less than a length in the vertical direction of an outer sidewall thereof facing the first blocking pattern.

公开(公告)号：US10797074B2

公开(公告)日：2020-10-06

申请号：US16379063

申请日：2019-04-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaehyun Yang ,  Bio Kim ,  Yujin Kim ,  Kyong-Won An ,  Sookyeom Yong ,  Junggeun Jee ,  Youngjun Cheon

IPC: H01L27/11578 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/11524

Abstract: A three-dimensional semiconductor memory device is provided. The device may include a first stack structure on a substrate including a cell array region and a connection region, a second stack structure on the first stack structure, a first vertical channel hole penetrating the first stack structure and partially exposing the substrate and a bottom surface of the second stack structure, on the cell array region, a second vertical channel hole penetrating the second stack structure and exposing the first vertical channel hole, on the cell array region, a bottom diameter of the second vertical channel hole being smaller than an top diameter of the first vertical channel hole, and a buffer pattern placed in the first vertical channel hole and adjacent to the bottom surface of the second stack structure.

公开(公告)号：US10720447B2

公开(公告)日：2020-07-21

申请号：US16512951

申请日：2019-07-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woo Jin Jang ,  Young Jin Noh ,  Jun Kyu Yang ,  Bio Kim ,  Kyong Won An

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L29/06 ,  H01L29/10 ,  H01L29/51 ,  H01L23/528 ,  H01L21/311 ,  H01L21/3115 ,  H01L21/02 ,  H01L23/522 ,  H01L21/28 ,  H01L27/11565

Abstract: An integrated circuit memory device includes a vertical stack structure containing an interlayer insulating layer and a gate electrode, on a substrate. A blocking dielectric region is provided on a sidewall of an opening in the stack structure. A lateral impurity region is provided, which extends between the blocking dielectric region and the interlayer insulating layer and between the blocking dielectric region and the gate electrode. A lower impurity region is also provided, which extends between the blocking dielectric region and the substrate.

公开(公告)号：US12048158B2

公开(公告)日：2024-07-23

申请号：US17722736

申请日：2022-04-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bio Kim ,  Yujin Kim ,  Philouk Nam ,  Youngseon Son ,  Kyongwon An ,  Jumi Yun ,  Woojin Jang

IPC: H10B43/27 ,  H01L21/02 ,  H01L21/28 ,  H01L29/423 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35

CPC classification number: H10B43/27 ,  H01L21/02249 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42324 ,  H01L29/4234 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35

Abstract: A vertical memory device includes a channel extending in a vertical direction on a substrate, a charge storage structure on an outer sidewall of the channel and including a tunnel insulation pattern, a charge trapping pattern, and a first blocking pattern sequentially stacked in a horizontal direction, and gate electrodes spaced apart from each other in the vertical direction, each of which surrounds the charge storage structure. The charge storage structure includes charge trapping patterns, each of which faces one of the gate electrodes in the horizontal direction. A length in the vertical direction of an inner sidewall of each of the charge trapping patterns facing the tunnel insulation pattern is less than a length in the vertical direction of an outer sidewall thereof facing the first blocking pattern.

公开(公告)号：US20200091186A1

公开(公告)日：2020-03-19

申请号：US16379063

申请日：2019-04-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaehyun YANG ,  Bio Kim ,  Yujin Kim ,  Kyong-Won An ,  Sookyeom Yong ,  Junggeun Jee ,  Youngjun Cheon

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157

Abstract: A three-dimensional semiconductor memory device is provided. The device may include a first stack structure on a substrate including a cell array region and a connection region, a second stack structure on the first stack structure, a first vertical channel hole penetrating the first stack structure and partially exposing the substrate and a bottom surface of the second stack structure, on the cell array region, a second vertical channel hole penetrating the second stack structure and exposing the first vertical channel hole, on the cell array region, a bottom diameter of the second vertical channel hole being smaller than an top diameter of the first vertical channel hole, and a buffer pattern placed in the first vertical channel hole and adjacent to the bottom surface of the second stack structure.

公开(公告)号：US20190341400A1

公开(公告)日：2019-11-07

申请号：US16512951

申请日：2019-07-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woo Jin Jang ,  Young Jin Noh ,  Jun Kyu Yang ,  Bio Kim ,  Kyong Won An

IPC: H01L27/11582 ,  H01L21/311 ,  H01L29/06 ,  H01L21/28 ,  H01L23/522 ,  H01L21/02 ,  H01L21/3115 ,  H01L27/1157 ,  H01L23/528 ,  H01L29/51 ,  H01L29/10

Abstract: An integrated circuit memory device includes a vertical stack structure containing an interlayer insulating layer and a gate electrode, on a substrate. A blocking dielectric region is provided on a sidewall of an opening in the stack structure. A lateral impurity region is provided, which extends between the blocking dielectric region and the interlayer insulating layer and between the blocking dielectric region and the gate electrode. A lower impurity region is also provided, which extends between the blocking dielectric region and the substrate.

公开(公告)号：US08765538B2

公开(公告)日：2014-07-01

申请号：US14061304

申请日：2013-10-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bio Kim ,  Kihyun Hwang ,  Jaeyoung Ahn ,  SeungHyun Lim ,  Dongwoo Kim

IPC: H01L21/336

CPC classification number: H01L29/66666 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/7889 ,  H01L29/7926

Abstract: Provided are three-dimensional semiconductor memory devices and methods of forming the same. The device includes a substrate, conductive patterns stacked on the substrate, and an active pattern penetrating the conductive patterns to be connected to the substrate. The active pattern may include a first doped region provided in an upper portion of the active pattern, and a diffusion-resistant doped region overlapped with at least a portion of the first doped region. The diffusion-resistant doped region may be a region doped with carbon.

Abstract translation: 提供三维半导体存储器件及其形成方法。 该器件包括衬底，堆叠在衬底上的导电图案，以及穿透要连接到衬底的导电图案的有源图案。 有源图案可以包括设置在有源图案的上部的第一掺杂区域和与第一掺杂区域的至少一部分重叠的扩散阻抗掺杂区域。 扩散阻止掺杂区域可以是掺杂有碳的区域。

公开(公告)号：US20230328985A1

公开(公告)日：2023-10-12

申请号：US18062251

申请日：2022-12-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangmin Kang ,  Bio Kim ,  Kyungwook Park

IPC: H10B43/27 ,  H10B41/10 ,  H10B41/35 ,  H10B41/40 ,  H10B41/27 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H01L23/522 ,  H01L23/528 ,  G11C5/06

CPC classification number: H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11556 ,  G11C5/06 ,  H01L27/1157 ,  H01L27/11573 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/11565

Abstract: A semiconductor device includes a peripheral circuit structure including: a first substrate, circuit devices on the first substrate, a lower wiring structure electrically connected to the circuit devices, a lower insulating layer covering the lower wiring structure, and a diffusion barrier layer on the lower insulating layer; and a memory cell structure including a second substrate including first and second regions on the peripheral circuit structure, gate electrodes stacked and spaced apart from each other in a first direction perpendicular to an upper surface of the second substrate in the first region and extending in a second direction perpendicular to the first direction to form a staircase shape in the second region, and channel structures penetrating the gate electrodes in the first direction and each including a channel layer. The diffusion barrier layer includes a first material layer having a hydrogen permeability lower than a hydrogen permeability of silicon nitride.