公开(公告)号：US11640649B2

公开(公告)日：2023-05-02

申请号：US16792875

申请日：2020-02-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Rahul Kumar ,  F N U Gurupad ,  David Tannenbaum

IPC: G06T3/40 ,  G06T15/40 ,  G06T15/80

Abstract: An interpolation method may include scheduling spatially adjacent image blocks for interpolation, and calculating ranges of values of an attribute of the image blocks, wherein at least one value for a first one of the image blocks may be used for a second one of the image blocks. Calculating the ranges of values may include calculating a root value of the attribute at a root location of an array of the spatially adjacent image blocks, and adding incremental values of the attribute to the root value at points of the image blocks that are offset from the root location. The root location may be centrally located in an array of the spatially adjacent image blocks. The interpolation may be calculated in a diagonal hierarchical manner based on a plane equation.

公开(公告)号：US11748933B2

公开(公告)日：2023-09-05

申请号：US17168168

申请日：2021-02-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keshavan Varadarajan ,  David C. Tannenbaum ,  F N U Gurupad

IPC: G06T1/20 ,  G06T15/00 ,  G06T15/80

CPC classification number: G06T15/005 ,  G06T1/20 ,  G06T15/80

Abstract: A GPU includes shader cores and a shader warp packer unit. The shader warp packer unit may receive a first primitive associated with a first partially covered quad, and a second primitive associated with a second partially covered quad. The shader warp packer unit may determine that the first partially covered quad and the second partially covered quad have non-overlapping coverage. The shader warp packer unit may pack the first partially covered quad and the second partially covered quad into a packed quad. The shader warp packer unit may send the packed quad to the shader cores. The first partially covered quad and the second partially covered quad may be spatially disjoint from each other. The shader cores may receive and process the packed quad with no loss of information relative to the shader cores individually processing the first partially covered quad and the second partially covered quad.

公开(公告)号：US11715252B2

公开(公告)日：2023-08-01

申请号：US17168168

申请日：2021-02-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keshavan Varadarajan ,  David C. Tannenbaum ,  F N U Gurupad

IPC: G06T1/20 ,  G06T15/00 ,  G06T15/80

CPC classification number: G06T15/005 ,  G06T1/20 ,  G06T15/80

Abstract: A GPU includes shader cores and a shader warp packer unit. The shader warp packer unit may receive a first primitive associated with a first partially covered quad, and a second primitive associated with a second partially covered quad. The shader warp packer unit may determine that the first partially covered quad and the second partially covered quad have non-overlapping coverage. The shader warp packer unit may pack the first partially covered quad and the second partially covered quad into a packed quad. The shader warp packer unit may send the packed quad to the shader cores. The first partially covered quad and the second partially covered quad may be spatially disjoint from each other. The shader cores may receive and process the packed quad with no loss of information relative to the shader cores individually processing the first partially covered quad and the second partially covered quad.