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公开(公告)号：US11748933B2
公开(公告)日：2023-09-05
申请号：US17168168
申请日：2021-02-04
Applicant: Samsung Electronics Co., Ltd.
Inventor： Keshavan Varadarajan , David C. Tannenbaum , F N U Gurupad
CPC classification number: G06T15/005 , G06T1/20 , G06T15/80
Abstract: A GPU includes shader cores and a shader warp packer unit. The shader warp packer unit may receive a first primitive associated with a first partially covered quad, and a second primitive associated with a second partially covered quad. The shader warp packer unit may determine that the first partially covered quad and the second partially covered quad have non-overlapping coverage. The shader warp packer unit may pack the first partially covered quad and the second partially covered quad into a packed quad. The shader warp packer unit may send the packed quad to the shader cores. The first partially covered quad and the second partially covered quad may be spatially disjoint from each other. The shader cores may receive and process the packed quad with no loss of information relative to the shader cores individually processing the first partially covered quad and the second partially covered quad.
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公开(公告)号：US20220301233A1
公开(公告)日：2022-09-22
申请号：US17576796
申请日：2022-01-14
Applicant: Samsung Electronics Co., Ltd.
Inventor： Keshavan Varadarajan , David C. Tannenbaum
Abstract: A hybrid ray tracing system includes: a processor; and memory including instructions that, when executed by the processor, cause the processor to: identify a subset of pixels of an image to be ray-traced based on variable rate shading (VRS) screenspace image data; set, based on the VRS screenspace image data, one or more material properties of at least one object corresponding to the subset of pixels; and perform ray-tracing for the subset of pixels to generate a ray-traced image. The ray-tracing includes performing a limited ray casting process based on the set one or more material properties.
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公开(公告)号：US12026799B2
公开(公告)日：2024-07-02
申请号：US17357964
申请日：2021-06-24
Applicant: Samsung Electronics Co., Ltd.
Inventor： Gabriel T. Dagani , Christopher P. Frascati , Fnu Gurupad , David Tannenbaum , Rama S. B. Harihara , Keshavan Varadarajan
CPC classification number: G06T1/20 , G06F9/485 , G06F9/4881
Abstract: A system and a method are disclosed improving forward progress of preempted workloads. A graphics pipeline processes tiles of a first low-priority job. A controller stops the first job by resetting the GPU and preempting the first job with a second job having a higher priority, determine whether the first job has been previously preempted one or more times, and adjust a batch-binning parameter reducing a likelihood that the first job will again be preempted in the current frame. In one embodiment, the controller is configured to stop the first job at a preemption boundary during a draw call or by resetting the GPU. A batch-binning parameter may include postponing sorting primitives into tiles during a binning process, increasing a number of tiles for backend rendering, reducing a quality of anti-aliasing, decreasing a shading rate quality, and/or decreasing input resolution and increasing upscaling of the first job.
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公开(公告)号：US11430080B2
公开(公告)日：2022-08-30
申请号：US16931435
申请日：2020-07-16
Applicant: Samsung Electronics Co., Ltd.
Inventor： Veynu Narasiman , David Tannenbaum , Keshavan Varadarajan
Abstract: A method of executing an early-Z draw call in a graphics processing pipeline may include detecting a late-Z draw call in the pipeline, determining a compatibility of a depth comparison function of the early-Z draw call with a depth comparison function of the late-Z draw call, and speculatively executing a fragment of the early-Z draw call with a shader. The method may further include determining that the fragment of the early-Z draw call passes the depth comparison function of the early-Z draw call, and updating a depth buffer with a depth value for the fragment of the early-Z draw call. The method may further include determining that the fragment of the early-Z draw call provides a correct result, and forwarding the speculative shader result for the fragment to a next stage of the pipeline.
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公开(公告)号：US09959661B2
公开(公告)日：2018-05-01
申请号：US15367507
申请日：2016-12-02
Applicant: Samsung Electronics Co., Ltd.
Inventor： Ankur Deshwal , Somya Singhal , Keshavan Varadarajan , Soma Kohli
CPC classification number: G06T15/005 , G06T1/20 , G06T11/40
Abstract: Provide are a methods and devices for processing graphics data in a graphics processing unit (GPU). The method of processing graphics data includes receiving, at a processor, a difference of Gaussian (DOG) layer of an image, detecting, from the received DOG layer, a candidate DOG layer of the image as an intermediate layer, detecting at least one extreme point by comparing values of the candidate DOG layer with values of a previous DOG layer and a next DOG layer, and storing the at least one extreme point in a buffer.
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Patent Agency Ranking
公开(公告)号：US09870639B2
公开(公告)日：2018-01-16
申请号：US14791626
申请日：2015-07-06
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Mookyoung Chung , Keshavan Varadarajan , Soojung Ryu , Jeongae Park , Seokyoon Jung
CPC classification number: G06T15/005 , G06T11/40
Abstract: Computing apparatus and methods are provided for performing a tile-based graphics pipeline. The graphics pipeline includes a binning pipeline configured to generate a tile list of objects indicating which tile vertices, primitives, or patches the objects belong to; and a rendering pipeline configured to render an object, per tile, based on the tile list generated in the binning pipeline. Each of the binning pipeline and the rendering pipeline is configured to implement a tessellation pipeline. The graphics pipeline may be configured to operate in an efficiency mode to defer or lower tessellation by performing tessellation in one of the binning and rendering pipelines or by setting a new lower tessellation factor.
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公开(公告)号：US11869117B2
公开(公告)日：2024-01-09
申请号：US17576796
申请日：2022-01-14
Applicant: Samsung Electronics Co., Ltd.
Inventor： Keshavan Varadarajan , David C. Tannenbaum
Abstract: A hybrid ray tracing system includes: a processor; and memory including instructions that, when executed by the processor, cause the processor to: identify a subset of pixels of an image to be ray-traced based on variable rate shading (VRS) screenspace image data; set, based on the VRS screenspace image data, one or more material properties of at least one object corresponding to the subset of pixels; and perform ray-tracing for the subset of pixels to generate a ray-traced image. The ray-tracing includes performing a limited ray casting process based on the set one or more material properties.
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公开(公告)号：US11276224B2
公开(公告)日：2022-03-15
申请号：US16930310
申请日：2020-07-15
Applicant: Samsung Electronics Co., Ltd.
Inventor： Keshavan Varadarajan , David Tannenbaum , Srinidhi Padmanabhan
Abstract: A system and a method are disclosed for ray tracing in a pipeline of a graphic processing unit (GPU). It is determined whether a ray bounce of a first ray intersects a first primitive that is the closest primitive intersected by the ray bounce. The first ray is part of a first group of rays being processed by a first single-instruction-multiple-data (SIMD) process. The first ray is assigned by a sorting or binning unit to a second group of rays based on the intersection of the first primitive. The second group of rays is processed by a second SIMD process. The first ray is assigned to the second group of rays based on a material identification of the first primitive, an identification of the first primitive intersected by the ray bound of the first ray, a pixel location, and a bounce number of the ray bounce intersecting the first primitive.
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公开(公告)号：US10559125B2
公开(公告)日：2020-02-11
申请号：US15366673
申请日：2016-12-01
Applicant: Samsung Electronics Co., Ltd.
Inventor： Ankur Deshwal , Vikash Kumar , Keshavan Varadarajan , Parikshit Kolipaka , Soma Kohli
IPC: G06T17/00
Abstract: A method and apparatus to construct a bounding volume hierarchy (BVH) tree includes: generating 2-dimensional (2D) tiles including primitives; converting the 2D tiles into 3-dimensional (3D) tiles; and constructing the BVH tree based on the 3D tiles.
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公开(公告)号：US11798218B2
公开(公告)日：2023-10-24
申请号：US17503259
申请日：2021-10-15
Applicant: Samsung Electronics Co., Ltd.
Inventor： Keshavan Varadarajan , Veynu Narasiman , David C. Tannenbaum
IPC: G06T15/00
CPC classification number: G06T15/005 , G06T2210/21
Abstract: A method of packing coverage in a graphics processing unit (GPU) may include receiving an indication for a portion of an image, determining, based on the indication, a packing technique for the portion of the image, and packing coverage for the portion of the image based on the packing technique. The indication may include one or more of: an importance, a quality, a level of interest, a level of detail, or a variable-rate shading (VRS) level. The indication may be received from an application. The packing technique may include array merging. The array merging may include quad merging. The packing technique may include pixel piling. The packing technique may be a first packing technique, and the method may further include determining, based on the indication, a second packing technique for the portion of the image, and packing coverage for the portion of the image based on the second packing technique.
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