公开(公告)号：US20220122912A1

公开(公告)日：2022-04-21

申请号：US17645866

申请日：2021-12-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： GEUNWON LIM

IPC: H01L23/522 ,  H01L27/11519 ,  H01L27/11548 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/11556

Abstract: A semiconductor device includes a substrate having a cell array region and a pad region, a stack structure including gate electrodes and mold insulating layers alternately stacked on the substrate and having a staircase shape in the pad region, first separation regions penetrating the stack structure in the pad region, extending in a first direction, and including first and second dummy insulating layers, the first dummy insulating layers covering side walls of the first separation regions and including horizontal portions covering portions of the gate electrodes, and the second dummy insulating layers disposed between the first dummy insulating layers, extending portions extending towards the mold insulating layers from the first dummy insulating layers in a second direction perpendicular to the first direction, second separation regions dividing the stack structure and extending in the first direction, and cell contact plugs penetrating the horizontal portions and connected to the gate electrodes.

公开(公告)号：US20220139456A1

公开(公告)日：2022-05-05

申请号：US17353918

申请日：2021-06-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： GEUNWON LIM ,  JINWOO PARK ,  ILGYU CHOI

IPC: G11C16/04 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

Abstract: Semiconductor devices may include a peripheral circuit structure including circuits, a substrate on the peripheral circuit structure, a pair of word line cut structures extending in a first direction on the substrate, and a memory cell block between the pair of word line cut structures and on the substrate. The memory cell block may include a memory stack structure including gate lines overlapping each other in a vertical direction, an interlayer insulation layer on an edge portion of each of the gate lines, a dam structure extending through the gate lines and the interlayer insulation layer, an intersection direction cut structure extending through the memory stack structure and the interlayer insulation layer in the vertical direction and being spaced apart from the dam structure, and a dummy channel structures between the intersection direction cut structure and the dam structure.

公开(公告)号：US20210134831A1

公开(公告)日：2021-05-06

申请号：US16902489

申请日：2020-06-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SEUNGMIN SONG ,  KANGMIN KIM ,  JOONGSHIK SHIN ,  GEUNWON LIM

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157

Abstract: A vertical memory device includes gate electrode structures, channels, first to third division patterns, and a first support layer. The gate electrode structure includes gate electrodes stacked in a first direction, and extends in a second direction. The gate electrode structures are spaced apart from one another in a third direction. The first division pattern extends in the second direction between the gate electrode structures. The second and third division patterns are alternately disposed in the second direction between the gate electrode structures. The first support layer is on the gate electrode structures at substantially the same height as upper portions of the first and second division patterns, and contacts the upper portions of the first and second division patterns. The upper portions of the first and second division patterns are arranged in a zigzag pattern in the second direction in a plan view.

公开(公告)号：US20200066742A1

公开(公告)日：2020-02-27

申请号：US16398442

申请日：2019-04-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： JUNHYOUNG KIM ,  KWANG-SOO KIM ,  GEUNWON LIM ,  JISUNG CHEON

IPC: H01L27/11565 ,  H01L27/11582 ,  H01L27/11573

Abstract: A three-dimensional semiconductor memory device may include a first stack block including first stacks arranged in a first direction on a substrate, a second stack block including second stacks arranged in the first direction on the substrate, and a separation structure provided on the substrate between the first stack block and the second stack block. The separation structure may include first mold layers and second mold layers, which are stacked in a vertical direction perpendicular to a top surface of the substrate.

公开(公告)号：US20220310651A1

公开(公告)日：2022-09-29

申请号：US17806842

申请日：2022-06-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SEUNGMIN SONG ,  KANGMIN KIM ,  JOONGSHIK SHIN ,  GEUNWON LIM

IPC: H01L27/11582

Abstract: A vertical memory device includes gate electrode structures, channels, first to third division patterns, and a first support layer. The gate electrode structure includes gate electrodes stacked in a first direction, and extends in a second direction. The gate electrode structures are spaced apart from one another in a third direction. The first division pattern extends in the second direction between the gate electrode structures. The second and third division patterns are alternately disposed in the second direction between the gate electrode structures. The first support layer is on the gate electrode structures at substantially the same height as upper portions of the first and second division patterns, and contacts the upper portions of the first and second division patterns. The upper portions of the first and second division patterns are arranged in a zigzag pattern in the second direction in a plan view.

公开(公告)号：US20220077167A1

公开(公告)日：2022-03-10

申请号：US17343330

申请日：2021-06-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： GEUNWON LIM ,  MINJUN KANG ,  BYUNGGON PARK ,  JOONGSHIK SHIN

IPC: H01L27/11526 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11573 ,  H01L27/11565 ,  G11C7/18 ,  H01L23/528

Abstract: A semiconductor includes a lower structure and a stack structure having interlayer insulating layers and horizontal layers alternately stacked on the lower structure. A first dam vertical structure penetrates the stack structure. The first dam vertical structure divides the stack structure into a gate stack region and an insulator stack region. The horizontal layers include gate horizontal layers in the gate stack region and insulating horizontal layers in the insulator stack region. A memory vertical structure and a supporter vertical structure penetrate the gate stack region. Separation structures penetrate the gate stack region. One separation structure includes a first side surface, a second side surface not perpendicular to the first side surface, and a connection side surface extending from the first side surface to the second side surface. The connection side surface is higher than an uppermost gate horizontal layer of the gate horizontal layers.

公开(公告)号：US20210327894A1

公开(公告)日：2021-10-21

申请号：US17359771

申请日：2021-06-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junhyoung Kim ,  Kwang-soo Kim ,  GEUNWON LIM ,  JISUNG CHEON

IPC: H01L27/11565 ,  H01L27/11582 ,  H01L27/11573

Abstract: A three-dimensional semiconductor memory device may include a first stack block including first stacks arranged in a first direction on a substrate, a second stack block including second stacks arranged in the first direction on the substrate, and a separation structure provided on the substrate between the first stack block and the second stack block. The separation structure may include first mold layers and second mold layers, which are stacked in a vertical direction perpendicular to a top surface of the substrate.