中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

9 records (took 0.027 seconds)

    Semiconductor device including vertical channel layer
    1.
    发明授权
    Semiconductor device including vertical channel layer 有权

    公开(公告)号：US10854630B2

    公开(公告)日：2020-12-01

    申请号：US16526139

    申请日：2019-07-30

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kwang-soo Kim ,  Yong-seok Kim ,  Tae-hun Kim ,  Min-kyung Bae ,  Jae-hoon Jang ,  Kohji Kanamori

    IPC: H01L27/11582 ,  H01L29/08 ,  H01L29/78 ,  H01L27/11565

    Abstract: A semiconductor device includes a plurality of channel structures on a substrate, each channel structure extending in a first direction perpendicular to the substrate, a common source extension structure including a first semiconductor layer having an n-type conductivity and a gate insulating layer between the substrate and the channel structures, a plurality of gate electrodes on the common source extension structure and spaced apart from each other on a sidewall of each of the channel structures in the first direction, and a common source region on the substrate in contact with the common source extension structure and including a second semiconductor layer having an n-type conductivity. An upper portion of the common source extension structure has a first width, and a lower portion of the common source extension structure has a second width smaller than the first width.

    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE
    2.
    发明申请
    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20210327894A1

    公开(公告)日：2021-10-21

    申请号：US17359771

    申请日：2021-06-28

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Junhyoung Kim ,  Kwang-soo Kim ,  GEUNWON LIM ,  JISUNG CHEON

    IPC: H01L27/11565 ,  H01L27/11582 ,  H01L27/11573

    Abstract: A three-dimensional semiconductor memory device may include a first stack block including first stacks arranged in a first direction on a substrate, a second stack block including second stacks arranged in the first direction on the substrate, and a separation structure provided on the substrate between the first stack block and the second stack block. The separation structure may include first mold layers and second mold layers, which are stacked in a vertical direction perpendicular to a top surface of the substrate.

    Semiconductor memory device
    3.
    发明授权
    Semiconductor memory device 有权

    公开(公告)号：US11107826B2

    公开(公告)日：2021-08-31

    申请号：US16565579

    申请日：2019-09-10

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hae-min Lee ,  Kwang-soo Kim ,  Sun-il Shim

    IPC: H01L27/1157 ,  G11C5/06 ,  H01L23/522 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/11556

    Abstract: A semiconductor memory device includes gate electrodes arranged on a substrate to be spaced apart from each other in a first direction perpendicular to an upper surface of the substrate, an upper insulation layer arranged on an uppermost gate electrode, channel structures penetrating through the upper insulation layer, and the gate electrodes in the first direction, and string selection line cut insulation layers horizontally separating the upper insulation layer and the uppermost gate electrode. Each of the string selection line cut insulation layers includes a protrusion protruding toward the uppermost gate electrode and positioning on the same level as the first gate electrode.

    Three-dimensional semiconductor memory devices
    4.
    发明授权
    Three-dimensional semiconductor memory devices 有权

    公开(公告)号：US10910396B2

    公开(公告)日：2021-02-02

    申请号：US16444716

    申请日：2019-06-18

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Junhyoung Kim ,  Geunwon Lim ,  Kwang-soo Kim

    IPC: H01L27/11575 ,  H01L23/522 ,  H01L27/11565 ,  H01L27/11582

    Abstract: A three-dimensional semiconductor memory device includes a plurality of first insulating layers vertically stacked on a peripheral logic structure, second insulating layers stacked alternately with the first insulating layers, conductive layers stacked alternately with the first insulating layers and disposed on sidewalls of the second insulating layers, through-interconnections penetrating the first insulating layers and the second insulating layers so as to be connected to the peripheral logic structure, and a first conductive line electrically connected to a plurality of first conductive layers of the conductive layers.

    Semiconductor device including vertical channel layer
    8.
    发明授权
    Semiconductor device including vertical channel layer 有权

    公开(公告)号：US10411033B2

    公开(公告)日：2019-09-10

    申请号：US15993756

    申请日：2018-05-31

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kwang-soo Kim ,  Yong-seok Kim ,  Tae-hun Kim ,  Min-kyung Bae ,  Jae-hoon Jang ,  Kohji Kanamori

    IPC: H01L27/11582 ,  H01L29/08 ,  H01L29/78

    Abstract: A semiconductor device includes a plurality of channel structures on a substrate, each channel structure extending in a first direction perpendicular to the substrate, and having a gate insulating layer and a channel layer, a common source extension region including a first semiconductor layer having an n-type conductivity between the substrate and the channel structures, a plurality of gate electrodes on the common source extension region and spaced apart from each other on a sidewall of each of the channel structures in the first direction, and a common source region on the substrate in contact with the common source extension region and including a second semiconductor layer having an n-type conductivity, wherein the gate insulating layer of each of the channel structures extends to cover an upper surface and at least a portion of a bottom surface of the common source extension region.

Patent Agency Ranking