公开(公告)号：US20220278101A1

公开(公告)日：2022-09-01

申请号：US17749211

申请日：2022-05-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Guyoung CHO ,  Subin SHIN ,  DONGHYUN ROH ,  Byung-Suk JUNG ,  SANGJIN HYUN

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/06 ,  H01L21/8238

Abstract: Disclosed is a semiconductor device comprising a substrate, a plurality of active patterns that protrude from the substrate, a device isolation layer between the active patterns, and a passivation layer that covers a top surface of the device isolation layer and exposes upper portions of the active patterns. The device isolation layer includes a plurality of first isolation parts adjacent to facing sidewalls of the active patterns, and a second isolation part between the first isolation parts. A top surface of the second isolation part is located at a lower level than that of top surfaces of the first isolation parts.

公开(公告)号：US20200006342A1

公开(公告)日：2020-01-02

申请号：US16273572

申请日：2019-02-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Guyoung CHO ,  Subin SHIN ,  DONGHYUN ROH ,  Byung-Suk JUNG ,  SANGJIN HYUN

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/06 ,  H01L21/8238

Abstract: Disclosed is a semiconductor device comprising a substrate, a plurality of active patterns that protrude from the substrate, a device isolation layer between the active patterns, and a passivation layer that covers a top surface of the device isolation layer and exposes upper portions of the active patterns. The device isolation layer includes a plurality of first isolation parts adjacent to facing sidewalls of the active patterns, and a second isolation part between the first isolation parts. A top surface of the second isolation part is located at a lower level than that of top surfaces of the first isolation parts.

公开(公告)号：US20230317728A1

公开(公告)日：2023-10-05

申请号：US18200986

申请日：2023-05-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Guyoung CHO ,  Subin SHIN ,  DONGHYUN ROH ,  Byung-Suk JUNG ,  SANGJIN HYUN

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L21/823821 ,  H01L29/0649 ,  H01L29/7851

Abstract: Disclosed is a semiconductor device comprising a substrate, a plurality of active patterns that protrude from the substrate, a device isolation layer between the active patterns, and a passivation layer that covers a top surface of the device isolation layer and exposes upper portions of the active patterns. The device isolation layer includes a plurality of first isolation parts adjacent to facing sidewalls of the active patterns, and a second isolation part between the first isolation parts. A top surface of the second isolation part is located at a lower level than that of top surfaces of the first isolation parts.