公开(公告)号：US20220278101A1

公开(公告)日：2022-09-01

申请号：US17749211

申请日：2022-05-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Guyoung CHO ,  Subin SHIN ,  DONGHYUN ROH ,  Byung-Suk JUNG ,  SANGJIN HYUN

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/06 ,  H01L21/8238

Abstract: Disclosed is a semiconductor device comprising a substrate, a plurality of active patterns that protrude from the substrate, a device isolation layer between the active patterns, and a passivation layer that covers a top surface of the device isolation layer and exposes upper portions of the active patterns. The device isolation layer includes a plurality of first isolation parts adjacent to facing sidewalls of the active patterns, and a second isolation part between the first isolation parts. A top surface of the second isolation part is located at a lower level than that of top surfaces of the first isolation parts.

公开(公告)号：US20250159952A1

公开(公告)日：2025-05-15

申请号：US18659659

申请日：2024-05-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeyoung Lim ,  HANSEONG KIM ,  DONGHYUN ROH ,  JoonYong Bae ,  GYUHWAN AHN ,  JANGHO LEE

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: A semiconductor device including an active pattern located on a substrate, spaced apart from other active patterns in a first direction and extending in a second direction different from the first direction; source/drain patterns located on the active pattern and each source drain pattern spaced apart from one another in the second direction; a channel pattern located between adjacent source/drain patterns; a gate pattern extending between the adjacent source/drain patterns in the first direction and surrounding at least a portion of the channel pattern; and an isolation structure extending in the first direction, the isolation structure located outside the source/drain pattern in the second direction and extending into the active pattern in a third direction different from the first and second directions, in which the isolation structure includes insulating patterns stacked in the third direction, an interfacial layer located between insulating patterns, and an insulating liner surrounding the insulating patterns.

公开(公告)号：US20200006342A1

公开(公告)日：2020-01-02

申请号：US16273572

申请日：2019-02-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Guyoung CHO ,  Subin SHIN ,  DONGHYUN ROH ,  Byung-Suk JUNG ,  SANGJIN HYUN

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/06 ,  H01L21/8238

Abstract: Disclosed is a semiconductor device comprising a substrate, a plurality of active patterns that protrude from the substrate, a device isolation layer between the active patterns, and a passivation layer that covers a top surface of the device isolation layer and exposes upper portions of the active patterns. The device isolation layer includes a plurality of first isolation parts adjacent to facing sidewalls of the active patterns, and a second isolation part between the first isolation parts. A top surface of the second isolation part is located at a lower level than that of top surfaces of the first isolation parts.

公开(公告)号：US20230352526A1

公开(公告)日：2023-11-02

申请号：US18350187

申请日：2023-07-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： GYUHWAN AHN ,  SUNG SOO KIM ,  CHAEHO NA ,  WOONGSIK NAM ,  DONGHYUN ROH

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/78 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/66 ,  H01L27/088

CPC classification number: H01L29/0653 ,  H01L29/0847 ,  H01L29/7851 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/78618 ,  H01L29/78696 ,  H01L21/02603 ,  H01L21/02532 ,  H01L21/76229 ,  H01L21/823431 ,  H01L21/823418 ,  H01L21/823481 ,  H01L21/823475 ,  H01L21/823412 ,  H01L29/66795 ,  H01L27/0886

Abstract: A semiconductor device includes first and second active patterns on a substrate, the first and second active patterns adjacent to each other in a first direction with a first trench between the first and second active patterns, third and fourth active patterns on the substrate, the third and fourth active patterns adjacent to each other in the first direction with a second trench between the third and fourth active patterns. The semiconductor device includes a first device isolation layer in the first trench, and a second device isolation layer in the second trench. A width of the second trench in the first direction is greater than a width of the first trench in the first direction. The second device isolation layer includes a first protrusion and a second protrusion which protrude from a top surface of the second device isolation layer.

公开(公告)号：US20220173212A1

公开(公告)日：2022-06-02

申请号：US17667996

申请日：2022-02-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： GYUHWAN AHN ,  SUNG SOO KIM ,  CHAEHO NA ,  WOONGSIK NAM ,  DONGHYUN ROH

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/78 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/66 ,  H01L27/088

Abstract: A semiconductor device includes first and second active patterns on a substrate, the first and second active patterns adjacent to each other in a first direction with a first trench between the first and second active patterns, third and fourth active patterns on the substrate, the third and fourth active patterns adjacent to each other in the first direction with a second trench between the third and fourth active patterns. The semiconductor device includes a first device isolation layer in the first trench, and a second device isolation layer in the second trench. A width of the second trench in the first direction is greater than a width of the first trench in the first direction. The second device isolation layer includes a first protrusion and a second protrusion which protrude from a top surface of the second device isolation layer.

公开(公告)号：US20230317728A1

公开(公告)日：2023-10-05

申请号：US18200986

申请日：2023-05-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Guyoung CHO ,  Subin SHIN ,  DONGHYUN ROH ,  Byung-Suk JUNG ,  SANGJIN HYUN

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L21/823821 ,  H01L29/0649 ,  H01L29/7851

Abstract: Disclosed is a semiconductor device comprising a substrate, a plurality of active patterns that protrude from the substrate, a device isolation layer between the active patterns, and a passivation layer that covers a top surface of the device isolation layer and exposes upper portions of the active patterns. The device isolation layer includes a plurality of first isolation parts adjacent to facing sidewalls of the active patterns, and a second isolation part between the first isolation parts. A top surface of the second isolation part is located at a lower level than that of top surfaces of the first isolation parts.

公开(公告)号：US20210118991A1

公开(公告)日：2021-04-22

申请号：US16903015

申请日：2020-06-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： GYUHWAN AHN ,  SUNG SOO KIM ,  CHAEHO NA ,  WOONGSIK NAM ,  DONGHYUN ROH

IPC: H01L29/06 ,  H01L27/088 ,  H01L29/08 ,  H01L29/78 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/66

Abstract: A semiconductor device includes first and second active patterns on a substrate, the first and second active patterns adjacent to each other in a first direction with a first trench between the first and second active patterns, third and fourth active patterns on the substrate, the third and fourth active patterns adjacent to each other in the first direction with a second trench between the third and fourth active patterns. The semiconductor device includes a first device isolation layer in the first trench, and a second device isolation layer in the second trench. A width of the second trench in the first direction is greater than a width of the first trench in the first direction. The second device isolation layer includes a first protrusion and a second protrusion which protrude from a top surface of the second device isolation layer.