公开(公告)号：US20250081467A1

公开(公告)日：2025-03-06

申请号：US18809742

申请日：2024-08-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： DONGJIN LEE ,  JAEDUK LEE ,  HAKSEON KIM ,  NAKJIN SON ,  KANG-OH YUN

IPC: H10B43/40 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27

Abstract: A semiconductor device according to an embodiment includes a semiconductor substrate, a plurality of transistors, a plurality of isolation portions, and a recess insulator. The semiconductor substrate includes a first transistor region and a second transistor region. The plurality of transistors includes a first transistor in the first transistor region and a second transistor in the second transistor region having larger operating voltage than the first transistor. Each isolation portion is at a boundary of a respective transistor of the plurality of transistors at a first surface of the semiconductor substrate. The recess insulator is disposed in the second transistor region at a second surface of the semiconductor substrate opposite to the first surface of the semiconductor substrate.

公开(公告)号：US20250048638A1

公开(公告)日：2025-02-06

申请号：US18432459

申请日：2024-02-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HAKSEON KIM ,  KANG-OH YUN ,  DONGJIN LEE ,  YOUNGROK KIM ,  RYOONGBIN LEE ,  JAEDUK LEE

IPC: H10B43/40 ,  G11C16/24 ,  H10B43/27

Abstract: Disclosed are a semiconductor device and an electronic system including the semiconductor device. The semiconductor device includes a semiconductor substrate including a plurality of trenches and silicon, a gate electrode positioned on the semiconductor substrate and between the trenches, and a source region and a drain region respectively positioned within the trenches. The source region and the drain region include silicon carbide (SiC) or gallium nitride (GaN), the source region and the drain region each includes a first lightly doped region and a second lightly doped region, and a whole of the first lightly doped region overlaps the second lightly doped region in a direction perpendicular to an upper surface of the semiconductor substrate.

公开(公告)号：US20250022798A1

公开(公告)日：2025-01-16

申请号：US18441071

申请日：2024-02-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： HAKSEON KIM ,  DONGJIN LEE ,  JAEDUK LEE ,  KANG-OH YUN

IPC: H01L23/528 ,  H01L23/522 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00

Abstract: According to an aspect of the present disclosure, a semiconductor device includes a peripheral structure, and a cell structure stacked on the peripheral structure. The cell structure includes a first substrate including a pad region and a cell region including a cell array region and an extending region, wherein the first substrate includes a first surface and a second surface opposite to the first surface, and wherein second surface faces the peripheral structure, a gate stacking structure including a plurality of gate electrodes and a plurality of interlayer insulating layers alternately stacked on the second surface of the first substrate, a channel structure disposed on the cell array region and penetrating the plurality of gate electrodes and the plurality of interlayer insulating layers, a plurality of gate contacts disposed on the extending region and connected to the plurality of gate electrodes, respectively, a cell insulation layer positioned over the second surface of the first substrate and covering the gate stacking structure, and an input/output contact disposed on the pad region and penetrating the cell insulation layer. The peripheral structure includes a second substrate electrically connected to the first substrate, a plurality of circuit elements positioned on the second substrate, a first barrier structure positioned over the second substrate and including a plurality of lower barrier layers, a plurality of first via holes disposed on the cell region and the pad region and penetrating at least one of the plurality of lower barrier layers, a plurality of second via holes disposed on the cell region and penetrating at least one of the plurality of lower barrier layers, and a plurality of contact vias positioned within the plurality of first via holes and connected to the plurality of circuit elements. In at least one lower barrier layer of the plurality of lower barrier layers, a sum of areas of at least one of the plurality of first via holes per unit area on the pad region is equal to a sum of areas of at least one of the plurality of first via holes on the cell region and areas of the plurality of second via holes per unit area on the cell region.

公开(公告)号：US20220208783A1

公开(公告)日：2022-06-30

申请号：US17387868

申请日：2021-07-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： JAE HWA SEO ,  HAKSEON KIM ,  SUNGKWEON BAEK

IPC: H01L27/11573 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582

Abstract: A semiconductor device and an electronic system including the same are disclosed. The semiconductor device may include a gate electrode on a semiconductor substrate, a gate insulating layer between the gate electrode and the semiconductor substrate, a first epitaxial layer disposed on the semiconductor substrate and at a side of the gate electrode, a second epitaxial layer disposed on the semiconductor substrate and at an opposite side of the gate electrode, a first contact plug in contact with a portion of the first epitaxial layer, and a second contact plug in contact with a portion of the second epitaxial layer. Top surfaces of the first and second epitaxial layers may be located at a level higher than a top surface of the gate electrode.