公开(公告)号：US20250081467A1

公开(公告)日：2025-03-06

申请号：US18809742

申请日：2024-08-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： DONGJIN LEE ,  JAEDUK LEE ,  HAKSEON KIM ,  NAKJIN SON ,  KANG-OH YUN

IPC: H10B43/40 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27

Abstract: A semiconductor device according to an embodiment includes a semiconductor substrate, a plurality of transistors, a plurality of isolation portions, and a recess insulator. The semiconductor substrate includes a first transistor region and a second transistor region. The plurality of transistors includes a first transistor in the first transistor region and a second transistor in the second transistor region having larger operating voltage than the first transistor. Each isolation portion is at a boundary of a respective transistor of the plurality of transistors at a first surface of the semiconductor substrate. The recess insulator is disposed in the second transistor region at a second surface of the semiconductor substrate opposite to the first surface of the semiconductor substrate.

公开(公告)号：US20220037502A1

公开(公告)日：2022-02-03

申请号：US17451691

申请日：2021-10-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： NAKJIN SON ,  SEUNGJOON LEE ,  BONG SEOB YANG ,  DOYOUNG CHOI

IPC: H01L29/49 ,  H01L29/786 ,  H01L21/02 ,  H01L21/28 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66

Abstract: A semiconductor device include a substrate including a peripheral region, a first active pattern provided on the peripheral region of the substrate, the first active pattern having an upper portion including first semiconductor patterns and second semiconductor patterns which are alternately stacked, a first gate electrode intersecting the first active pattern, a pair of first source/drain patterns provided at both sides of the first gate electrode, respectively, and a first gate insulating layer disposed between the first gate electrode and the first active pattern. The first gate insulating layer includes a first insulating layer formed on the first active pattern, a second insulating layer formed on the first insulating layer, and a high-k dielectric layer formed on the second insulating layer. The first gate insulating layer contains a first dipole element including lanthanum (La), aluminum (Al), or a combination thereof.