公开(公告)号：US20210043556A1

公开(公告)日：2021-02-11

申请号：US16877945

申请日：2020-05-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： MIJI LEE ,  TAEYOUNG JEONG ,  YOONKYEONG JO ,  SANGWOO PAE ,  HWASUNG RHEE

IPC: H01L23/528 ,  H01L23/522 ,  H01L29/417 ,  H01L29/78 ,  H01L21/768

Abstract: A semiconductor device includes a lower wiring, an upper wiring on the lower wiring, and a via between the lower wiring and the upper wiring. The lower wiring has a first end surface and a second end surface opposing each other, the upper wiring has a third end surface and a fourth end surface opposing each other, and the via has a first side adjacent to the second end surface of the lower wiring and a second side adjacent to the third end surface of the upper wiring. A distance between a lower end of the first side of the via and an upper end of the second end surface of the lower wiring is less than ⅓ of a width of a top surface of the via, and a distance between an upper end of the second side of the via and an upper end of the third end surface of the upper wiring is less than ⅓ of the width of the top surface of the via.

公开(公告)号：US20220148965A1

公开(公告)日：2022-05-12

申请号：US17648829

申请日：2022-01-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： MIJI LEE ,  TAEYOUNG JEONG ,  YOONKYEONG JO ,  SANGWOO PAE ,  HWASUNG RHEE

IPC: H01L23/522 ,  H01L23/528

Abstract: A semiconductor device includes a lower wiring, an upper wiring on the lower wiring, and a via between the lower wiring and the upper wiring. The lower wiring has a first end surface and a second end surface opposing each other, the upper wiring has a third end surface and a fourth end surface opposing each other, and the via has a first side adjacent to the second end surface of the lower wiring and a second side adjacent to the third end surface of the upper wiring. A distance between a lower end of the first side of the via and an upper end of the second end surface of the lower wiring is less than ⅓ of a width of a top surface of the via, and a distance between an upper end of the second side of the via and an upper end of the third end surface of the upper wiring is less than ⅓ of the width of the top surface of the via.

公开(公告)号：US20140339559A1

公开(公告)日：2014-11-20

申请号：US14261513

申请日：2014-04-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： PING HSUN SU ,  YOONHAE KIM ,  HWASUNG RHEE

IPC: H01L21/66

CPC classification number: H01L22/34

Abstract: A semiconductor device is provided. First and second pads are electrically connected to a plurality of test structures. Each test structure includes an active region, active patterns, gate electrodes and an electrode pattern. The active region includes a rounded corner portion. The active patterns protrudes from the semiconductor substrate and extends in parallel in a first direction. The gate electrodes crosses over the active patterns in a second direction. One gate electrode is electrically connected to the first pad. The electrode pattern is disposed at a side of the gate electrode electrically connected to the first pad. The electrode pattern is electrically connected to the second pad. The electrode pattern crosses over the active patterns. An overlapping area of the electrode pattern and the active patterns in each test structure is different from an overlapping area of the electrode pattern and the active patterns in other test structures.

Abstract translation: 提供半导体器件。 第一和第二焊盘电连接到多个测试结构。 每个测试结构包括有源区，有源图案，栅电极和电极图案。 活动区域包括圆角部分。 有源图案从半导体衬底突出并沿第一方向平行延伸。 栅电极在第二方向上跨过有源图案。 一个栅电极电连接到第一焊盘。 电极图案设置在与第一焊盘电连接的栅电极的一侧。 电极图案电连接到第二垫。 电极图案穿过有源图案。 每个测试结构中的电极图案和活性图案的重叠区域与其他测试结构中的电极图案和活动图案的重叠区域不同。