公开(公告)号：US20210043556A1

公开(公告)日：2021-02-11

申请号：US16877945

申请日：2020-05-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： MIJI LEE ,  TAEYOUNG JEONG ,  YOONKYEONG JO ,  SANGWOO PAE ,  HWASUNG RHEE

IPC: H01L23/528 ,  H01L23/522 ,  H01L29/417 ,  H01L29/78 ,  H01L21/768

Abstract: A semiconductor device includes a lower wiring, an upper wiring on the lower wiring, and a via between the lower wiring and the upper wiring. The lower wiring has a first end surface and a second end surface opposing each other, the upper wiring has a third end surface and a fourth end surface opposing each other, and the via has a first side adjacent to the second end surface of the lower wiring and a second side adjacent to the third end surface of the upper wiring. A distance between a lower end of the first side of the via and an upper end of the second end surface of the lower wiring is less than ⅓ of a width of a top surface of the via, and a distance between an upper end of the second side of the via and an upper end of the third end surface of the upper wiring is less than ⅓ of the width of the top surface of the via.

公开(公告)号：US20220148965A1

公开(公告)日：2022-05-12

申请号：US17648829

申请日：2022-01-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： MIJI LEE ,  TAEYOUNG JEONG ,  YOONKYEONG JO ,  SANGWOO PAE ,  HWASUNG RHEE

IPC: H01L23/522 ,  H01L23/528

Abstract: A semiconductor device includes a lower wiring, an upper wiring on the lower wiring, and a via between the lower wiring and the upper wiring. The lower wiring has a first end surface and a second end surface opposing each other, the upper wiring has a third end surface and a fourth end surface opposing each other, and the via has a first side adjacent to the second end surface of the lower wiring and a second side adjacent to the third end surface of the upper wiring. A distance between a lower end of the first side of the via and an upper end of the second end surface of the lower wiring is less than ⅓ of a width of a top surface of the via, and a distance between an upper end of the second side of the via and an upper end of the third end surface of the upper wiring is less than ⅓ of the width of the top surface of the via.