公开(公告)号：US20190130059A1

公开(公告)日：2019-05-02

申请号：US16233422

申请日：2018-12-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JONGWOOK JEON ,  YEOIL YUN ,  SANGWOO PAE ,  UIHUI KWON ,  KEUNHO LEE

IPC: G06F17/50

Abstract: A method of designing a semiconductor circuit using a circuit simulation tool executed by a computer includes calculating power consumptions of elements of the semiconductor circuit by use of the circuit simulation tool. A thermal netlist is created about the semiconductor circuit, based on the power consumptions and geometry information of each of the elements. A simulation of the semiconductor circuit is performed with the thermal netlist using the circuit simulation tool to detect a temperature of each of the elements. The thermal netlist includes thermal capacitance information of each of the elements.

公开(公告)号：US20220301969A1

公开(公告)日：2022-09-22

申请号：US17505953

申请日：2021-10-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunggyun NOH ,  GUN-HEE BAE ,  SANGWOO PAE ,  JINSOO BAE ,  DEOK-SEON CHOI ,  IL-JOO CHOI

IPC: H01L23/367 ,  H01L23/22 ,  H01L23/40

Abstract: A semiconductor package device includes a package substrate, an interposer on the package substrate, a semiconductor package on the interposer, and an under-fill between the interposer and the semiconductor package. The interposer includes at least one first trench at an upper portion of the interposer that extends in a first direction parallel to a top surface of the package substrate. The at least one first trench vertically overlaps an edge region of the semiconductor package. The under-fill fills at least a portion of the at least one trench.

公开(公告)号：US20220148965A1

公开(公告)日：2022-05-12

申请号：US17648829

申请日：2022-01-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： MIJI LEE ,  TAEYOUNG JEONG ,  YOONKYEONG JO ,  SANGWOO PAE ,  HWASUNG RHEE

IPC: H01L23/522 ,  H01L23/528

Abstract: A semiconductor device includes a lower wiring, an upper wiring on the lower wiring, and a via between the lower wiring and the upper wiring. The lower wiring has a first end surface and a second end surface opposing each other, the upper wiring has a third end surface and a fourth end surface opposing each other, and the via has a first side adjacent to the second end surface of the lower wiring and a second side adjacent to the third end surface of the upper wiring. A distance between a lower end of the first side of the via and an upper end of the second end surface of the lower wiring is less than ⅓ of a width of a top surface of the via, and a distance between an upper end of the second side of the via and an upper end of the third end surface of the upper wiring is less than ⅓ of the width of the top surface of the via.

公开(公告)号：US20190294748A1

公开(公告)日：2019-09-26

申请号：US16280205

申请日：2019-02-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JONGWOOK JEON ,  YEOIL YUN ,  SANGWOO PAE ,  UIHUI KWON ,  KEUNHO LEE

IPC: G06F17/50

Abstract: A method of designing a semiconductor circuit using a circuit simulation tool executed by a computer includes calculating power consumptions of elements of the semiconductor circuit by use of the circuit simulation tool. A thermal netlist is created about the semiconductor circuit, based on the power consumptions and geometry information of each of the elements. A simulation of the semiconductor circuit is performed with the thermal netlist using the circuit simulation tool to detect a temperature of each of the elements. The thermal netlist includes thermal capacitance information of each of the elements.

公开(公告)号：US20240074154A1

公开(公告)日：2024-02-29

申请号：US18126395

申请日：2023-03-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seonhaeng LEE ,  SANGWOO PAE ,  NAMHYUN LEE

IPC: H10B12/00

CPC classification number: H10B12/34 ,  H10B12/053 ,  H10B12/09 ,  H10B12/315 ,  H10B12/50

Abstract: A semiconductor memory may include a substrate, a buried dielectric layer on the substrate and providing a first recess that extends in a first direction, a word line in the first recess of the buried dielectric layer, first and second source/drain patterns on opposite sides of the word line, a channel pattern between the word line and the first recess of the buried dielectric layer and contacting the first and second source/drain patterns, and a bit line electrically connected to the second source/drain pattern and extending in a second direction that intersects the first direction. The channel pattern includes vertical parts and a horizontal part connected to each other. The vertical parts are on opposite lateral surfaces of the word line. The horizontal part is below the word line.

公开(公告)号：US20230028943A1

公开(公告)日：2023-01-26

申请号：US17680877

申请日：2022-02-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HYUNGGYUN NOH ,  SANGWOO PAE ,  JINSOO BAE ,  ILJOO CHOI ,  DEOKSEON CHOI ,  KEUNHO RHEW

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31

Abstract: A semiconductor package includes; a package substrate including an upper surface with a bonding pad, a lower semiconductor chip disposed on the upper surface of the package substrate, wherein an upper surface of the lower semiconductor chip includes a connect edge region including a connection pad and an open edge region including a dam structure including dummy bumps, a bonding wire having a first height above the upper surface of the lower semiconductor chip and connecting the bonding pad and the connection pad, an upper semiconductor chip disposed on the upper surface of the lower semiconductor chip using an inter-chip bonding layer, and a molding portion on the package substrate and substantially surrounding the lower semiconductor chip and the upper semiconductor chip.

公开(公告)号：US20210043556A1

公开(公告)日：2021-02-11

申请号：US16877945

申请日：2020-05-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： MIJI LEE ,  TAEYOUNG JEONG ,  YOONKYEONG JO ,  SANGWOO PAE ,  HWASUNG RHEE

IPC: H01L23/528 ,  H01L23/522 ,  H01L29/417 ,  H01L29/78 ,  H01L21/768

Abstract: A semiconductor device includes a lower wiring, an upper wiring on the lower wiring, and a via between the lower wiring and the upper wiring. The lower wiring has a first end surface and a second end surface opposing each other, the upper wiring has a third end surface and a fourth end surface opposing each other, and the via has a first side adjacent to the second end surface of the lower wiring and a second side adjacent to the third end surface of the upper wiring. A distance between a lower end of the first side of the via and an upper end of the second end surface of the lower wiring is less than ⅓ of a width of a top surface of the via, and a distance between an upper end of the second side of the via and an upper end of the third end surface of the upper wiring is less than ⅓ of the width of the top surface of the via.