公开(公告)号：US09891856B2

公开(公告)日：2018-02-13

申请号：US14953642

申请日：2015-11-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Won-Hyung Song ,  Duk-Sung Kim ,  Hoki Kim ,  Soo-Woong Ahn ,  Ha-Ryong Yoon ,  Ju-Yun Jung

IPC: G06F12/06 ,  G06F3/06 ,  G11C8/12 ,  G11C7/10

CPC classification number: G06F3/0638 ,  G06F3/0604 ,  G06F3/0629 ,  G06F3/0683 ,  G11C7/10 ,  G11C8/12

Abstract: A memory system includes an address remapping circuit and a first set of memory devices. The address remapping circuit includes a plurality of input terminals for receiving a plurality of chip selection signals and a plurality of chip identification signals. The address remapping circuit receives input signals corresponding to a portion of the plurality of chip selection signals and the plurality of chip identification signals through corresponding input terminals of the plurality of input terminals and generates a plurality of internal chip selection signals based on the input signals and a remapping control signal. Each of the first set of memory devices is configured to be selected in response to a corresponding internal chip selection signal of the plurality of internal chip selection signals.