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公开(公告)号:US20240233609A9
公开(公告)日:2024-07-11
申请号:US18466892
申请日:2023-09-14
Applicant: Samsung Electronics Co., Ltd.
Inventor: Ying-Da Chang , Chulho Choi , Yu-Chieh Huang , Ching-Chieh Wu , Hajoon Shin , Zhen-Guo Ding , Jia-Way Chen , Kyunlyeol Lee , Yongjoo Song
IPC: G09G3/20
CPC classification number: G09G3/2096 , G09G2310/0267 , G09G2310/0291 , G09G2320/0626 , G09G2320/0673
Abstract: A gamma tap circuit includes: (i) a first gamma division circuit configured to generate a first gamma tap voltage by performing voltage division of an upper gamma tap voltage and a lower gamma tap voltage, in-sync with a first clock signal CK1 and a first complementary clock signal CK1b, which is 180° out-of-phase relative to CK1, (ii) a second gamma division circuit configured to generate a second gamma tap voltage by performing voltage division of the upper gamma tap voltage and the first gamma tap voltage, in-sync with a second clock signal CK2 and a second complementary clock signal CK2b, which is 180° out-of-phase relative to CK2, and (iii) a third gamma division circuit configured to generate a third gamma tap voltage by performing voltage division of the first gamma tap voltage and the lower gamma tap voltage, in response to CK2 and CK2b, which have a lower frequency relative to CK1 and CK1b.
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公开(公告)号:US11521534B2
公开(公告)日:2022-12-06
申请号:US17519724
申请日:2021-11-05
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Shih Chiao Huang , Jinwoo Kim , Tao-Jung Hung , Chulho Choi , Hajoon Shin , Myungho Seo , Yongjoo Song , Shih-Hsiung Kuo , Chui-Hsun Chiu , Jia Wei Chen , Chao Hsuan Liu , Yu-Wen Chiou
IPC: G09G3/20
Abstract: A display driving integrated circuit includes a common voltage buffer configured to provide a common voltage to a display panel and when a line outputting the common voltage and a gate line are short-circuited, apply a first current to the gate line or receive a second current from the gate line; a current generator configured to sum currents respectively corresponding to the first current and the second current and output an output current obtained by the summing; and a current detector configured to convert the output current into an output voltage and output a high or low signal based on a result of comparing the output voltage with a preset voltage.
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公开(公告)号:US12020618B2
公开(公告)日:2024-06-25
申请号:US17990179
申请日:2022-11-18
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Chulho Choi , Yu-Chieh Huang , Hajoon Shin , Han-Chiang Su , Jia-Way Chen , Kyunlyeol Lee , Yi-Chien Wen , Yongjoo Song , Shih-Chiao Huang
IPC: G09G3/20
CPC classification number: G09G3/20 , G09G2310/0251 , G09G2310/0275 , G09G2320/0223
Abstract: The present disclosure provides methods, apparatuses, and non-transitory computer-readable mediums for setting charge sharing times, which may be adaptable to a display panel. In some embodiments, the apparatus includes a pixel array and a source driver configured to drive each column of the pixel array. In some embodiments, a setting method of charge sharing times includes grouping a plurality of pixels of a pixel array in a row direction to form a plurality of pixel groups. The setting method further includes setting a charge sharing time of each pixel group of the plurality of pixel groups according to a quantity of pixel groups in the plurality of pixel groups. A charge sharing time of a pixel group located closest to a source driver in the pixel array is greater than a charge sharing time of a pixel group located farthest from the source driver in the pixel array.
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公开(公告)号:US12159567B2
公开(公告)日:2024-12-03
申请号:US18466892
申请日:2023-09-14
Applicant: Samsung Electronics Co., Ltd.
Inventor: Ying-Da Chang , Chulho Choi , Yu-Chieh Huang , Ching-Chieh Wu , Hajoon Shin , Zhen-Guo Ding , Jia-Way Chen , Kyunlyeol Lee , Yongjoo Song
Abstract: A gamma tap circuit includes: (i) a first gamma division circuit configured to generate a first gamma tap voltage by performing voltage division of an upper gamma tap voltage and a lower gamma tap voltage, in-sync with a first clock signal CK1 and a first complementary clock signal CK1b, which is 180° out-of-phase relative to CK1, (ii) a second gamma division circuit configured to generate a second gamma tap voltage by performing voltage division of the upper gamma tap voltage and the first gamma tap voltage, in-sync with a second clock signal CK2 and a second complementary clock signal CK2b, which is 180° out-of-phase relative to CK2, and (iii) a third gamma division circuit configured to generate a third gamma tap voltage by performing voltage division of the first gamma tap voltage and the lower gamma tap voltage, in response to CK2 and CK2b, which have a lower frequency relative to CK1 and CK1b.
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公开(公告)号:US20240135859A1
公开(公告)日:2024-04-25
申请号:US18466892
申请日:2023-09-13
Applicant: Samsung Electronics Co., Ltd.
Inventor: Ying-Da Chang , Chulho Choi , Yu-Chieh Huang , Ching-Chieh Wu , Hajoon Shin , Zhen-Guo Ding , Jia-Way Chen , Kyunlyeol Lee , Yongjoo Song
IPC: G09G3/20
CPC classification number: G09G3/2096 , G09G2310/0267 , G09G2310/0291 , G09G2320/0626 , G09G2320/0673
Abstract: A gamma tap circuit includes: (i) a first gamma division circuit configured to generate a first gamma tap voltage by performing voltage division of an upper gamma tap voltage and a lower gamma tap voltage, in-sync with a first clock signal CK1 and a first complementary clock signal CK1b, which is 180° out-of-phase relative to CK1, (ii) a second gamma division circuit configured to generate a second gamma tap voltage by performing voltage division of the upper gamma tap voltage and the first gamma tap voltage, in-sync with a second clock signal CK2 and a second complementary clock signal CK2b, which is 180° out-of-phase relative to CK2, and (iii) a third gamma division circuit configured to generate a third gamma tap voltage by performing voltage division of the first gamma tap voltage and the lower gamma tap voltage, in response to CK2 and CK2b, which have a lower frequency relative to CK1 and CK1b.
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