公开(公告)号：US12020618B2

公开(公告)日：2024-06-25

申请号：US17990179

申请日：2022-11-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chulho Choi ,  Yu-Chieh Huang ,  Hajoon Shin ,  Han-Chiang Su ,  Jia-Way Chen ,  Kyunlyeol Lee ,  Yi-Chien Wen ,  Yongjoo Song ,  Shih-Chiao Huang

IPC: G09G3/20

CPC classification number: G09G3/20 ,  G09G2310/0251 ,  G09G2310/0275 ,  G09G2320/0223

Abstract: The present disclosure provides methods, apparatuses, and non-transitory computer-readable mediums for setting charge sharing times, which may be adaptable to a display panel. In some embodiments, the apparatus includes a pixel array and a source driver configured to drive each column of the pixel array. In some embodiments, a setting method of charge sharing times includes grouping a plurality of pixels of a pixel array in a row direction to form a plurality of pixel groups. The setting method further includes setting a charge sharing time of each pixel group of the plurality of pixel groups according to a quantity of pixel groups in the plurality of pixel groups. A charge sharing time of a pixel group located closest to a source driver in the pixel array is greater than a charge sharing time of a pixel group located farthest from the source driver in the pixel array.

公开(公告)号：US12254844B2

公开(公告)日：2025-03-18

申请号：US18213632

申请日：2023-06-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jiyong Jeong ,  Yongjoo Song ,  Jeongah Ahn ,  Hajun Lee ,  Youngsub Jin

IPC: G09G3/3233 ,  G09G3/3225 ,  G09G3/3258 ,  G09G3/3275 ,  G09G3/3291 ,  G09G3/36 ,  H10K50/805

Abstract: A display driving circuit is provided. The circuit drives a display panel that includes data lines, sensing lines, and sub-pixels connected to the data lines and the sensing lines. The display driving circuit includes a data driver integrated circuit that drives the data lines. The data driver integrated circuit includes a driving block and a sensing block. The driving block includes plural digital-analog converters (DACs) each performing digital-analog conversion with respect to received sub-pixel data to generate output voltages and provide the output voltages of the DACs to the data lines. The sensing block measures grayscale voltages output from the DACs in a first operation mode and measures pixel voltages of the sub-pixels received from the sensing lines in a second operation mode.

公开(公告)号：US20240233609A9

公开(公告)日：2024-07-11

申请号：US18466892

申请日：2023-09-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ying-Da Chang ,  Chulho Choi ,  Yu-Chieh Huang ,  Ching-Chieh Wu ,  Hajoon Shin ,  Zhen-Guo Ding ,  Jia-Way Chen ,  Kyunlyeol Lee ,  Yongjoo Song

IPC: G09G3/20

CPC classification number: G09G3/2096 ,  G09G2310/0267 ,  G09G2310/0291 ,  G09G2320/0626 ,  G09G2320/0673

Abstract: A gamma tap circuit includes: (i) a first gamma division circuit configured to generate a first gamma tap voltage by performing voltage division of an upper gamma tap voltage and a lower gamma tap voltage, in-sync with a first clock signal CK1 and a first complementary clock signal CK1b, which is 180° out-of-phase relative to CK1, (ii) a second gamma division circuit configured to generate a second gamma tap voltage by performing voltage division of the upper gamma tap voltage and the first gamma tap voltage, in-sync with a second clock signal CK2 and a second complementary clock signal CK2b, which is 180° out-of-phase relative to CK2, and (iii) a third gamma division circuit configured to generate a third gamma tap voltage by performing voltage division of the first gamma tap voltage and the lower gamma tap voltage, in response to CK2 and CK2b, which have a lower frequency relative to CK1 and CK1b.

公开(公告)号：US11756470B2

公开(公告)日：2023-09-12

申请号：US18061616

申请日：2022-12-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chulho Choi ,  Yongjoo Song

IPC: G09G3/20

CPC classification number: G09G3/20 ,  G09G2300/0408 ,  G09G2310/0267

Abstract: A display device includes a display panel including data lines configured to receive an image signal, gate lines configured to receive a scan signal, and gate connection lines configured to transmit the scan signal to the gate lines; and a multi-chip film package including, on a film, a first gate integrated circuit (IC) configured to transmit a first scan signal to the gate connection lines through first gate output lines, a second gate IC configured to transmit a second scan signal to the gate connection lines through second gate output lines, and a source IC configured to transmit the image signal to the data lines through source output lines. Each of the first gate output lines is between two adjacent source output lines, and each of the second gate output lines is between two adjacent source output lines.

公开(公告)号：US11727888B2

公开(公告)日：2023-08-15

申请号：US16803042

申请日：2020-02-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jiyong Jeong ,  Yongjoo Song ,  Jeongah Ahn ,  Hajun Lee ,  Youngsub Jin

IPC: G09G3/3291 ,  G09G3/3233 ,  G09G3/36

CPC classification number: G09G3/3291 ,  G09G2310/027

Abstract: A display driving circuit is provided. The circuit drives a display panel that includes data lines, sensing lines, and sub-pixels connected to the data lines and the sensing lines. The display driving circuit includes a data driver integrated circuit that drives the data lines. The data driver integrated circuit includes a driving block and a sensing block. The driving block includes plural digital-analog converters (DACs) each performing digital-analog conversion with respect to received sub-pixel data to generate output voltages and provide the output voltages of the DACs to the data lines. The sensing block measures grayscale voltages output from the DACs in a first operation mode and measures pixel voltages of the sub-pixels received from the sensing lines in a second operation mode.

公开(公告)号：US11521534B2

公开(公告)日：2022-12-06

申请号：US17519724

申请日：2021-11-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Shih Chiao Huang ,  Jinwoo Kim ,  Tao-Jung Hung ,  Chulho Choi ,  Hajoon Shin ,  Myungho Seo ,  Yongjoo Song ,  Shih-Hsiung Kuo ,  Chui-Hsun Chiu ,  Jia Wei Chen ,  Chao Hsuan Liu ,  Yu-Wen Chiou

IPC: G09G3/20

Abstract: A display driving integrated circuit includes a common voltage buffer configured to provide a common voltage to a display panel and when a line outputting the common voltage and a gate line are short-circuited, apply a first current to the gate line or receive a second current from the gate line; a current generator configured to sum currents respectively corresponding to the first current and the second current and output an output current obtained by the summing; and a current detector configured to convert the output current into an output voltage and output a high or low signal based on a result of comparing the output voltage with a preset voltage.

公开(公告)号：US11574608B2

公开(公告)日：2023-02-07

申请号：US17361755

申请日：2021-06-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Beophee Kim ,  Sungjin Lim ,  Yongjoo Song ,  Chulho Choi ,  Hanchiang Su ,  Yichien Wen

IPC: G09G3/36

Abstract: A display apparatus includes a display panel including a plurality of horizontal lines each including a plurality of pixels, a timing controller configured to output a polarity control signal representing a polarity corresponding to each of the plurality of horizontal lines and having a value inverted by n horizontal line units, and a source driver configured to generate a timing pulse signal sequentially representing a data charging time of each of the plurality of horizontal lines and to output a data voltage, having a polarity corresponding to each of the plurality of horizontal lines, to the display panel on the basis of the timing pulse signal. When a value of the polarity control signal is inverted, the source driver generates the timing pulse signal including a data charging time corresponding to a count value obtained by counting a number of horizontal lines after a polarity is inverted.

公开(公告)号：US11288992B2

公开(公告)日：2022-03-29

申请号：US16811881

申请日：2020-03-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Ho Lee ,  Jinwoo Kim ,  Yongjoo Song

IPC: G09G3/20

Abstract: A display driving circuit includes a gamma generator configured to output, to nodes, gamma voltages having different voltage levels, and a selector configured to select one of the nodes to which the gamma voltages are output, and output a voltage of the selected one of the nodes. The display driving circuit further includes a voltage regulator configured to selectively input a first current to the selected one of the nodes and output a second current from the selected one of the nodes, based on the voltage of the selected one of the nodes, to adjust a voltage level of the voltage of the selected one of the nodes to a voltage level of a respective one of the gamma voltages that is output to the selected one of the nodes.

公开(公告)号：US10600383B2

公开(公告)日：2020-03-24

申请号：US15686317

申请日：2017-08-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongjoo Song ,  Pan-soo Kim ,  Jin-woo Kim ,  Ju-hyun Ko

IPC: G09G3/36 ,  H03F3/30 ,  H03F3/45

Abstract: A source driver includes an interpolation amplifier configured to generate an interpolation voltage based on a received plurality of input voltages and output the interpolation voltage to a display panel; and an input selector configured to receive a first voltage and a second voltage having a different level from the first voltage, and configured to selectively provide at least one of the first and second voltages as the plurality of input voltages in response to some of the lower bits of pixel data. The interpolation amplifier includes four conductive differential input pairs configured to receive four input voltages from among the plurality of input voltages, respectively. Each of the first differential input pair and third differential input pair comprises a first type transistor. Each of the second differential input pair and fourth differential input pair comprises a second type transistor.

公开(公告)号：US12159567B2

公开(公告)日：2024-12-03

申请号：US18466892

申请日：2023-09-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ying-Da Chang ,  Chulho Choi ,  Yu-Chieh Huang ,  Ching-Chieh Wu ,  Hajoon Shin ,  Zhen-Guo Ding ,  Jia-Way Chen ,  Kyunlyeol Lee ,  Yongjoo Song

IPC: G09G3/20 ,  G09G3/36

Abstract: A gamma tap circuit includes: (i) a first gamma division circuit configured to generate a first gamma tap voltage by performing voltage division of an upper gamma tap voltage and a lower gamma tap voltage, in-sync with a first clock signal CK1 and a first complementary clock signal CK1b, which is 180° out-of-phase relative to CK1, (ii) a second gamma division circuit configured to generate a second gamma tap voltage by performing voltage division of the upper gamma tap voltage and the first gamma tap voltage, in-sync with a second clock signal CK2 and a second complementary clock signal CK2b, which is 180° out-of-phase relative to CK2, and (iii) a third gamma division circuit configured to generate a third gamma tap voltage by performing voltage division of the first gamma tap voltage and the lower gamma tap voltage, in response to CK2 and CK2b, which have a lower frequency relative to CK1 and CK1b.