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公开(公告)号:US11605714B2
公开(公告)日:2023-03-14
申请号:US16353750
申请日:2019-03-14
发明人: Dong Kak Lee , Min Woo Kim , Bong Hyun Kim , Hee Young Park , Seo Jin Ahn , Won Yong Lee
IPC分类号: H01L29/40 , H01L29/10 , H01L21/762 , H01L27/108
摘要: A semiconductor device includes a trench defining an active region in a substrate, a first insulating layer on a bottom surface and side surfaces of the active region inside the trench, a shielding layer on a surface of the first insulating layer, the shielding layer including a plurality of spaced apart particles, a second insulating layer on the shielding layer and having first charge trapped therein, the plurality of spaced apart particles being configured to concentrate second charge having an opposite polarity to the charge trapped in the second insulating layer, and a gap-fill insulating layer on the second insulating layer in the trench.
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公开(公告)号:US20230197789A1
公开(公告)日:2023-06-22
申请号:US18169327
申请日:2023-02-15
发明人: Dong Kak Lee , Min Woo Kim , Bong Hyun Kim , Hee Young Park , Seo Jin Ahn , Won Yong Lee
IPC分类号: H01L29/10 , H01L21/762 , H10B12/00
CPC分类号: H01L29/1083 , H01L21/76224 , H10B12/34 , H10B12/31
摘要: A semiconductor device includes a trench defining an active region in a substrate, a first insulating layer on a bottom surface and side surfaces of the active region inside the trench, a shielding layer on a surface of the first insulating layer, the shielding layer including a plurality of spaced apart particles, a second insulating layer on the shielding layer and having first charge trapped therein, the plurality of spaced apart particles being configured to concentrate second charge having an opposite polarity to the charge trapped in the second insulating layer, and a gap-fill insulating layer on the second insulating layer in the trench.
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公开(公告)号:US20230128492A1
公开(公告)日:2023-04-27
申请号:US18049732
申请日:2022-10-26
发明人: Seongkeun CHO , Hee Young Park , Jin Hyung Park , Kun Tack Lee , Jung Hyuk Jang , Chun Hyung Chung
IPC分类号: H01L27/108
摘要: There is provided a semiconductor memory device capable of improving the performance and/or the reliability of a device. The semiconductor memory device includes a substrate having a cell area and a peripheral area defined along a periphery of the cell area, wherein the cell area includes an active area defined by a cell element separation film, a cell area separation film in the substrate and defining the cell area, and a plurality of storage contacts connected to the active area, and arranged along a first direction. The plurality of storage contacts includes a first storage contact, a second storage contact, and a third storage contact, wherein the second storage contact is between the first storage contact and the third storage contact, each of the first storage contact and the third storage contact contains or surrounds or defines an airgap, and the second storage contact is free of an airgap.
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