公开(公告)号：US20140183599A1

公开(公告)日：2014-07-03

申请号：US14133064

申请日：2013-12-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soohun Hong ,  Heesoo Kang ,  Dongho Cha

IPC: H01L29/78

CPC classification number: H01L29/785 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/7848

Abstract: Field effect transistors are provided. An active region protrudes from a substrate and a gate electrode is provided on the active region. Source/drain regions are provided at both sides of the active region under the gate electrode, respectively. A width of a lower portion of the gate electrode is greater than a width of an upper portion of the gate electrode.

Abstract translation: 提供场效应晶体管。 有源区域从衬底突出，并且栅极电极设置在有源区域上。 源极/漏极区分别设置在栅电极下方的有源区的两侧。 栅电极的下部的宽度大于栅电极的上部的宽度。

公开(公告)号：US10128154B2

公开(公告)日：2018-11-13

申请号：US15674185

申请日：2017-08-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Heedon Jeong ,  Jae Yup Chung ,  Heesoo Kang ,  Donghyun Kim ,  Sanghyuk Hong ,  Soohun Hong

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/285 ,  H01L21/3213 ,  H01L27/088

Abstract: A semiconductor device includes a fin region with long and short sides, a first field insulating layer including a top surface lower than that of the fin region and adjacent to a side surface of the short side of the fin region, a second field insulating layer including a top surface lower than that of the fin region and adjacent to a side surface of the long side of the fin region, an etch barrier pattern on the first field insulating layer, a first gate on the fin region and the second field insulating layer to face a top surface of the fin region and side surfaces of the long sides of the fin region. A second gate is on the etch barrier pattern overlapping the first field insulating layer. A source/drain region is between the first gate and the second gate, in contact with the etch barrier pattern.

公开(公告)号：US09123774B2

公开(公告)日：2015-09-01

申请号：US14162481

申请日：2014-01-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Dae Suk ,  Heesoo Kang ,  Sungil Park ,  Changwoo Oh

IPC: H01L29/66 ,  H01L29/40 ,  H01L21/3205 ,  H01L21/764 ,  H01L29/78

CPC classification number: H01L21/764 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: Provided is a semiconductor device, which includes a gate electrode crossing over a semiconductor fin disposed on a substrate, a gate dielectric layer disposed between the gate electrode and the semiconductor fin, a channel region having a three dimensional structure defined in the semiconductor fin under the gate electrode, impurity regions disposed in the semiconductor fin at both sides of the gate electrode and spaced apart from the gate electrode, a first interlayer dielectric layer covering an entire surface of the substrate, except for the gate electrode, first contact plugs passing through the first interlayer dielectric layer and contacting the impurity regions, and a second interlayer dielectric layer covering the gate electrode and partially filling a space between the gate electrode and the impurity regions to define an air gap between the gate electrode and the impurity regions.

Abstract translation: 提供了一种半导体器件，其包括跨越设置在衬底上的半导体翅片上的栅极电极，设置在栅极电极和半导体鳍片之间的栅极电介质层，具有限定在半导体鳍片下方的三维结构的沟道区域 栅极电极，设置在栅电极两侧并与栅电极间隔开的半导体鳍片中的杂质区域，除了栅电极之外覆盖基板整个表面的第一层间电介质层，穿过第 第一层间电介质层和与杂质区接触的第二层间电介质层和覆盖栅电极并部分地填充栅电极和杂质区之间的空间的第二层间电介质层，以限定栅电极和杂质区之间的气隙。

公开(公告)号：US09735059B2

公开(公告)日：2017-08-15

申请号：US14830199

申请日：2015-08-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Heedon Jeong ,  Jae Yup Chung ,  Heesoo Kang ,  Donghyun Kim ,  Sanghyuk Hong ,  Soohun Hong

IPC: H01L21/8234 ,  H01L29/78 ,  H01L21/02 ,  H01L21/285 ,  H01L21/3213 ,  H01L29/66 ,  H01L27/088

CPC classification number: H01L21/823431 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/28518 ,  H01L21/32139 ,  H01L21/823418 ,  H01L21/823437 ,  H01L27/0886 ,  H01L29/66545 ,  H01L29/7831 ,  H01L29/7855

Abstract: A semiconductor device includes a fin region with long and short sides, a first field insulating layer including a top surface lower than that of the fin region and adjacent to a side surface of the short side of the fin region, a second field insulating layer including a top surface lower than that of the fin region and adjacent to a side surface of the long side of the fin region, an etch barrier pattern on the first field insulating layer, a first gate on the fin region and the second field insulating layer to face a top surface of the fin region and side surfaces of the long sides of the fin region. A second gate is on the etch barrier pattern overlapping the first field insulating layer. A source/drain region is between the first gate and the second gate, in contact with the etch barrier pattern.

公开(公告)号：US09269813B2

公开(公告)日：2016-02-23

申请号：US14133064

申请日：2013-12-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soohun Hong ,  Heesoo Kang ,  Dongho Cha

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/165

CPC classification number: H01L29/785 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/7848

Abstract: Field effect transistors are provided. An active region protrudes from a substrate and a gate electrode is provided on the active region. Source/drain regions are provided at both sides of the active region under the gate electrode, respectively. A width of a lower portion of the gate electrode is greater than a width of an upper portion of the gate electrode.

Abstract translation: 提供场效应晶体管。 有源区域从衬底突出，并且栅极电极设置在有源区域上。 源极/漏极区分别设置在栅电极下方的有源区的两侧。 栅电极的下部的宽度大于栅电极的上部的宽度。

公开(公告)号：US09117910B2

公开(公告)日：2015-08-25

申请号：US14313435

申请日：2014-06-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Heedon Jeong ,  Jae Yup Chung ,  Heesoo Kang ,  Donghyun Kim ,  Sanghyuk Hong ,  Soohun Hong

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823431 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/28518 ,  H01L21/32139 ,  H01L21/823418 ,  H01L21/823437 ,  H01L27/0886 ,  H01L29/66545 ,  H01L29/7831 ,  H01L29/7855

Abstract: A semiconductor device includes a fin region with long and short sides, a first field insulating layer including a top surface lower than that of the fin region and adjacent to a side surface of the short side of the fin region, a second field insulating layer including a top surface lower than that of the fin region and adjacent to a side surface of the long side of the fin region, an etch barrier pattern on the first field insulating layer, a first gate on the fin region and the second field insulating layer to face a top surface of the fin region and side surfaces of the long sides of the fin region. A second gate is on the etch barrier pattern overlapping the first field insulating layer. A source/drain region is between the first gate and the second gate, in contact with the etch barrier pattern.

Abstract translation: 半导体器件包括具有短边和短边的鳍片区域，第一场绝缘层，其包括比翅片区域低的顶表面，并且与鳍片区域的短边的侧表面相邻;第二场绝缘层，包括 与翅片区域相比较靠近散热片区域的长边侧表面的顶表面，第一场绝缘层上的蚀刻阻挡图案，鳍状区域上的第一栅极和第二场绝缘层， 面对翅片区域的顶表面和翅片区域的长边的侧表面。 第二栅极位于与第一场绝缘层重叠的蚀刻阻挡图案上。 源极/漏极区在第一栅极和第二栅极之间，与蚀刻阻挡图案接触。

公开(公告)号：US20140203348A1

公开(公告)日：2014-07-24

申请号：US14162481

申请日：2014-01-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Dae Suk ,  Heesoo Kang ,  Sungil Park ,  Changwoo Oh

IPC: H01L29/06 ,  H01L29/78

CPC classification number: H01L21/764 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: Provided is a semiconductor device, which includes a gate electrode crossing over a semiconductor fin disposed on a substrate, a gate dielectric layer disposed between the gate electrode and the semiconductor fin, a channel region having a three dimensional structure defined in the semiconductor fin under the gate electrode, impurity regions disposed in the semiconductor fin at both sides of the gate electrode and spaced apart from the gate electrode, a first interlayer dielectric layer covering an entire surface of the substrate, except for the gate electrode, first contact plugs passing through the first interlayer dielectric layer and contacting the impurity regions, and a second interlayer dielectric layer covering the gate electrode and partially filling a space between the gate electrode and the impurity regions to define an air gap between the gate electrode and the impurity regions.

Abstract translation: 提供了一种半导体器件，其包括跨越设置在衬底上的半导体翅片上的栅极电极，设置在栅极电极和半导体鳍片之间的栅极电介质层，具有限定在半导体鳍片下方的三维结构的沟道区域 栅极电极，设置在栅电极两侧并与栅电极间隔开的半导体鳍片中的杂质区域，除了栅电极之外覆盖基板整个表面的第一层间电介质层，穿过第 第一层间电介质层和与杂质区接触的第二层间电介质层和覆盖栅电极并部分地填充栅电极和杂质区之间的空间的第二层间电介质层，以限定栅电极和杂质区之间的气隙。