公开(公告)号：US20160087026A1

公开(公告)日：2016-03-24

申请号：US14718685

申请日：2015-05-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myung Gil Kang ,  Dongwon Kim ,  Ilryong Kim ,  Changwoo Oh ,  Keun Hwi Cho ,  Toshinori Fukai

IPC: H01L49/02 ,  H01L27/06

CPC classification number: H01L28/20 ,  H01L27/0629

Abstract: Embodiments of the inventive concepts provide a resistor and a semiconductor device including the same. The resistor includes a substrate, a device isolation layer in the substrate which defines active regions arranged in a first direction a resistance layer including resistance patterns that vertically protrude from the active regions and are connected to each other in the first direction, and contact electrodes on the resistance layer.

Abstract translation: 本发明构思的实施例提供一种电阻器和包括该电阻器的半导体器件。 电阻器包括衬底，衬底中的器件隔离层，其限定在第一方向上布置的有源区，包括从有源区垂直突出并在第一方向上彼此连接的电阻图案的电阻层，以及接触电极 电阻层。

公开(公告)号：US09123774B2

公开(公告)日：2015-09-01

申请号：US14162481

申请日：2014-01-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Dae Suk ,  Heesoo Kang ,  Sungil Park ,  Changwoo Oh

IPC: H01L29/66 ,  H01L29/40 ,  H01L21/3205 ,  H01L21/764 ,  H01L29/78

CPC classification number: H01L21/764 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: Provided is a semiconductor device, which includes a gate electrode crossing over a semiconductor fin disposed on a substrate, a gate dielectric layer disposed between the gate electrode and the semiconductor fin, a channel region having a three dimensional structure defined in the semiconductor fin under the gate electrode, impurity regions disposed in the semiconductor fin at both sides of the gate electrode and spaced apart from the gate electrode, a first interlayer dielectric layer covering an entire surface of the substrate, except for the gate electrode, first contact plugs passing through the first interlayer dielectric layer and contacting the impurity regions, and a second interlayer dielectric layer covering the gate electrode and partially filling a space between the gate electrode and the impurity regions to define an air gap between the gate electrode and the impurity regions.

Abstract translation: 提供了一种半导体器件，其包括跨越设置在衬底上的半导体翅片上的栅极电极，设置在栅极电极和半导体鳍片之间的栅极电介质层，具有限定在半导体鳍片下方的三维结构的沟道区域 栅极电极，设置在栅电极两侧并与栅电极间隔开的半导体鳍片中的杂质区域，除了栅电极之外覆盖基板整个表面的第一层间电介质层，穿过第 第一层间电介质层和与杂质区接触的第二层间电介质层和覆盖栅电极并部分地填充栅电极和杂质区之间的空间的第二层间电介质层，以限定栅电极和杂质区之间的气隙。

公开(公告)号：US20180331201A1

公开(公告)日：2018-11-15

申请号：US16026749

申请日：2018-07-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Choong-Ho Lee ,  Donggu Yi ,  Seung Chul Lee ,  Hyungsuk Lee ,  Seonah Nam ,  Changwoo Oh ,  Jongwook Lee ,  Song-Yi Han

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L27/092 ,  H01L21/762 ,  H01L21/3205 ,  H01L29/51

CPC classification number: H01L29/6681 ,  H01L21/02255 ,  H01L21/32053 ,  H01L21/76224 ,  H01L27/092 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: Provided are field effect transistors and methods of fabricating the same. The transistor may include a substrate with an active pattern, the active pattern having a top surface and two sidewalls, a gate electrode proximal to the top surface and the sidewalls of the active pattern and crossing the active pattern, a gate spacer covering a sidewall of the gate electrode, a gate dielectric pattern at a bottom surface of the gate electrode, a source electrode on the active pattern at one side of the gate electrode, a drain electrode on the active pattern at another side of the gate electrode, and silicide patterns on surfaces of the source and drain electrodes, respectively. The gate dielectric pattern includes at least one high-k layer and the gate spacer has a dielectric constant that is smaller than that of the gate dielectric pattern.

公开(公告)号：US20140203348A1

公开(公告)日：2014-07-24

申请号：US14162481

申请日：2014-01-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Dae Suk ,  Heesoo Kang ,  Sungil Park ,  Changwoo Oh

IPC: H01L29/06 ,  H01L29/78

CPC classification number: H01L21/764 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: Provided is a semiconductor device, which includes a gate electrode crossing over a semiconductor fin disposed on a substrate, a gate dielectric layer disposed between the gate electrode and the semiconductor fin, a channel region having a three dimensional structure defined in the semiconductor fin under the gate electrode, impurity regions disposed in the semiconductor fin at both sides of the gate electrode and spaced apart from the gate electrode, a first interlayer dielectric layer covering an entire surface of the substrate, except for the gate electrode, first contact plugs passing through the first interlayer dielectric layer and contacting the impurity regions, and a second interlayer dielectric layer covering the gate electrode and partially filling a space between the gate electrode and the impurity regions to define an air gap between the gate electrode and the impurity regions.

Abstract translation: 提供了一种半导体器件，其包括跨越设置在衬底上的半导体翅片上的栅极电极，设置在栅极电极和半导体鳍片之间的栅极电介质层，具有限定在半导体鳍片下方的三维结构的沟道区域 栅极电极，设置在栅电极两侧并与栅电极间隔开的半导体鳍片中的杂质区域，除了栅电极之外覆盖基板整个表面的第一层间电介质层，穿过第 第一层间电介质层和与杂质区接触的第二层间电介质层和覆盖栅电极并部分地填充栅电极和杂质区之间的空间的第二层间电介质层，以限定栅电极和杂质区之间的气隙。

公开(公告)号：US09653551B2

公开(公告)日：2017-05-16

申请号：US14980134

申请日：2015-12-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changwoo Oh ,  Myung Gil Kang ,  Bomsoo Kim ,  Jongshik Yoon

IPC: H01L27/12 ,  H01L29/10 ,  H01L21/84 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/78 ,  H01L27/092 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/1041 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/063 ,  H01L29/0649 ,  H01L29/0676 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/785

Abstract: Field effect transistors are provided. According to the field effect transistor, a source region and a drain region are provided on a substrate and a fin portion is provided to protrude from the substrate. The fin portion connects the source region and the drain region to each other. A gate electrode pattern is disposed on the fin portion and extends to cross over the fin portion. A gate dielectric layer is disposed between the fin portion and the gate electrode pattern. A semiconductor layer is disposed between the fin portion and the gate dielectric layer. The semiconductor layer and the fin portion have dopant-concentrations different from each other, respectively.

公开(公告)号：US09520458B2

公开(公告)日：2016-12-13

申请号：US14718685

申请日：2015-05-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myung Gil Kang ,  Dongwon Kim ,  Ilryong Kim ,  Changwoo Oh ,  Keun Hwi Cho ,  Toshinori Fukai

IPC: H01L27/11 ,  H01L49/02 ,  H01L27/06

CPC classification number: H01L28/20 ,  H01L27/0629

Abstract: Embodiments of the inventive concepts provide a resistor and a semiconductor device including the same. The resistor includes a substrate, a device isolation layer in the substrate which defines active regions arranged in a first direction a resistance layer including resistance patterns that vertically protrude from the active regions and are connected to each other in the first direction, and contact electrodes on the resistance layer.

Abstract translation: 本发明构思的实施例提供一种电阻器和包括该电阻器的半导体器件。 电阻器包括衬底，衬底中的器件隔离层，其限定在第一方向上布置的有源区，包括从有源区垂直突出并在第一方向上彼此连接的电阻图案的电阻层，以及接触电极 电阻层。

公开(公告)号：US09252274B2

公开(公告)日：2016-02-02

申请号：US14579222

申请日：2014-12-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myung Gil Kang ,  Changwoo Oh ,  Heedon Jeong ,  Chiwon Cho

IPC: H01L29/78 ,  H01L29/10 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L21/823821 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851 ,  H01L29/7856

Abstract: A Field Effect Transistor (FET) structure may include a fin on a substrate having a first lattice constant and at least two different lattice constant layers on respective different axially oriented surfaces of the fin, wherein the at least two different lattice constant layers each comprise lattice constants that are different than the first lattice constant and each other.

公开(公告)号：US20150108545A1

公开(公告)日：2015-04-23

申请号：US14579222

申请日：2014-12-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myung Gil Kang ,  Changwoo Oh ,  Heedon Jeong ,  Chiwon Cho

IPC: H01L29/78

CPC classification number: H01L29/785 ,  H01L21/823821 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851 ,  H01L29/7856

Abstract: A Field Effect Transistor (FET) structure may include a fin on a substrate having a first lattice constant and at least two different lattice constant layers on respective different axially oriented surfaces of the fin, wherein the at least two different lattice constant layers each comprise lattice constants that are different than the first lattice constant and each other.

Abstract translation: 场效应晶体管（FET）结构可以包括在鳍的相应不同轴向取向表面上的具有第一晶格常数和至少两个不同晶格常数层的衬底上的鳍，其中所述至少两个不同的晶格常数层各自包括晶格 与第一晶格常数不同的常数和彼此。