SEMICONDUCTOR DEVICES COMPRISING FAILURE DETECTORS FOR DETECTING FAILURE OF BIPOLAR JUNCTION TRANSISTORS AND METHODS FOR DETECTING FAILURE OF THE BIPOLAR JUNCTION TRANSISTORS

    公开(公告)号:US20250085329A1

    公开(公告)日:2025-03-13

    申请号:US18958291

    申请日:2024-11-25

    Abstract: A semiconductor device may include a voltage generator configured to generate a first base-emitter voltage of a first bipolar junction transistor, and a failure detector configured to generate a failure signal by comparing the first base-emitter voltage with an upper limit reference voltage and a lower limit reference voltage. The failure detector may include a second bipolar junction transistor a current source configured to generate a bias current, a first resistor coupled between the current source and a emitter of the second bipolar junction transistor to generate the upper limit reference voltage, a second resistor and a third resistor configured to divide a second base-emitter voltage of the second bipolar junction transistor to generate the lower limit reference voltage, and a first and second comparator configured to compare the first base-emitter voltage with the upper limit reference voltage and the lower limit reference voltage, respectively, to generate respective failure signals.

    Semiconductor devices comprising failure detectors for detecting failure of bipolar junction transistors and methods for detecting failure of the bipolar junction transistors

    公开(公告)号:US12181512B2

    公开(公告)日:2024-12-31

    申请号:US17984332

    申请日:2022-11-10

    Abstract: A semiconductor device may include a voltage generator configured to generate a first base-emitter voltage of a first bipolar junction transistor, and a failure detector configured to generate a failure signal by comparing the first base-emitter voltage with an upper limit reference voltage and a lower limit reference voltage. The failure detector may include a second bipolar junction transistor a current source configured to generate a bias current, a first resistor coupled between the current source and a emitter of the second bipolar junction transistor to generate the upper limit reference voltage, a second resistor and a third resistor configured to divide a second base-emitter voltage of the second bipolar junction transistor to generate the lower limit reference voltage, and a first and second comparator configured to compare the first base-emitter voltage with the upper limit reference voltage and the lower limit reference voltage, respectively, to generate respective failure signals.

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