Laser detecting circuit and semiconductor apparatus including the same

    公开(公告)号:US12230588B2

    公开(公告)日:2025-02-18

    申请号:US17860699

    申请日:2022-07-08

    Abstract: A laser detecting circuit is provided. The laser detecting circuit includes a latch circuit with a first inverter configured to invert a first output signal at a first node to generate a second output signal at a second node, and a second inverter configured to generate the first output signal based on the second output signal. The second inverter includes a plurality of PMOS transistors connected in series between a first source voltage and the first node, and a plurality of NMOS transistors. A gate of each of the plurality of PMOS transistors is connected to the second node, and a drain of each of the plurality of NMOS transistors is connected to the first node. The plurality of NMOS transistors includes dummy NMOS transistors and normal NMOS transistors.

    Semiconductor devices comprising failure detectors for detecting failure of bipolar junction transistors and methods for detecting failure of the bipolar junction transistors

    公开(公告)号:US12181512B2

    公开(公告)日:2024-12-31

    申请号:US17984332

    申请日:2022-11-10

    Abstract: A semiconductor device may include a voltage generator configured to generate a first base-emitter voltage of a first bipolar junction transistor, and a failure detector configured to generate a failure signal by comparing the first base-emitter voltage with an upper limit reference voltage and a lower limit reference voltage. The failure detector may include a second bipolar junction transistor a current source configured to generate a bias current, a first resistor coupled between the current source and a emitter of the second bipolar junction transistor to generate the upper limit reference voltage, a second resistor and a third resistor configured to divide a second base-emitter voltage of the second bipolar junction transistor to generate the lower limit reference voltage, and a first and second comparator configured to compare the first base-emitter voltage with the upper limit reference voltage and the lower limit reference voltage, respectively, to generate respective failure signals.

    GLITCH DETECTOR, SECURITY DEVICE INCLUDING THE SAME AND ELECTRONIC SYSTEM INCLUDING THE SAME

    公开(公告)号:US20220137104A1

    公开(公告)日:2022-05-05

    申请号:US17314693

    申请日:2021-05-07

    Abstract: A glitch detector includes a sensing circuit, a glitch-to-pulse generator and a comparing circuit. The sensing circuit generates a glitch voltage and at least one reference voltage based on a first power supply voltage. The glitch-to-pulse generator receives the first power supply voltage or the glitch voltage, and generates at least one pulse voltage including a pulse when the glitch occurs on the first power supply voltage. The comparing circuit generates at least one detection voltage by comparing the glitch voltage with the at least one reference voltage based on the pulse included in the at least one pulse voltage. The at least one detection voltage is activated when the glitch occurs on the first power supply voltage.

    Glitch detector, security device including the same and electronic system including the same

    公开(公告)号:US11486912B2

    公开(公告)日:2022-11-01

    申请号:US17314693

    申请日:2021-05-07

    Abstract: A glitch detector includes a sensing circuit, a glitch-to-pulse generator and a comparing circuit. The sensing circuit generates a glitch voltage and at least one reference voltage based on a first power supply voltage. The glitch-to-pulse generator receives the first power supply voltage or the glitch voltage, and generates at least one pulse voltage including a pulse when the glitch occurs on the first power supply voltage. The comparing circuit generates at least one detection voltage by comparing the glitch voltage with the at least one reference voltage based on the pulse included in the at least one pulse voltage. The at least one detection voltage is activated when the glitch occurs on the first power supply voltage.

    DEFENSE CIRCUIT OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE INCLUDING THE SAME

    公开(公告)号:US20210210439A1

    公开(公告)日:2021-07-08

    申请号:US16995925

    申请日:2020-08-18

    Abstract: A semiconductor device includes a sensing circuit including a first semiconductor element configured to generate a first current in response to externally incident light, a compensation circuit including a semiconductor element configured to generate a second current depending on an ambient temperature and to remove the second current from the first current to generate a third current, a detection circuit configured to convert the third current into a photovoltage and to compare the photovoltage with a predetermined reference voltage to determine whether an external attack has occurred, and a defense circuit configured to control the semiconductor device to perform a predetermined defense operation, based on a result of the determination.

    SEMICONDUCTOR DEVICES COMPRISING FAILURE DETECTORS FOR DETECTING FAILURE OF BIPOLAR JUNCTION TRANSISTORS AND METHODS FOR DETECTING FAILURE OF THE BIPOLAR JUNCTION TRANSISTORS

    公开(公告)号:US20250085329A1

    公开(公告)日:2025-03-13

    申请号:US18958291

    申请日:2024-11-25

    Abstract: A semiconductor device may include a voltage generator configured to generate a first base-emitter voltage of a first bipolar junction transistor, and a failure detector configured to generate a failure signal by comparing the first base-emitter voltage with an upper limit reference voltage and a lower limit reference voltage. The failure detector may include a second bipolar junction transistor a current source configured to generate a bias current, a first resistor coupled between the current source and a emitter of the second bipolar junction transistor to generate the upper limit reference voltage, a second resistor and a third resistor configured to divide a second base-emitter voltage of the second bipolar junction transistor to generate the lower limit reference voltage, and a first and second comparator configured to compare the first base-emitter voltage with the upper limit reference voltage and the lower limit reference voltage, respectively, to generate respective failure signals.

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