公开(公告)号：US20210246044A1

公开(公告)日：2021-08-12

申请号：US17229031

申请日：2021-04-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki Wook JUNG ,  Dong Oh KIM ,  Seok Han PARK ,  Chan Sic YOON ,  Ki Seok LEE ,  Ho In LEE ,  Ju Yeon JANG ,  Je Min PARK ,  Jin Woo HONG

IPC: C01G23/053

Abstract: A semiconductor device and method for fabricating the same are provided. The semiconductor device includes a substrate including a cell region, a core region, and a boundary region between the cell region and the core region, a boundary element isolation layer in the boundary region of the substrate to separate the cell region from the core region, a high-k dielectric layer on at least a part of the boundary element isolation layer and the core region of the substrate, a first work function metal pattern comprising a first extension overlapping the boundary element isolation layer on the high-k dielectric layer, and a second work function metal pattern comprising a second extension overlapping the boundary element isolation layer on the first work function metal pattern, wherein a first length of the first extension is different from a second length of the second extension.

公开(公告)号：US20180226411A1

公开(公告)日：2018-08-09

申请号：US15828934

申请日：2017-12-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki Wook JUNG ,  Dong Oh KIM ,  Seok Han PARK ,  Chan Sic YOON ,  Ki Seok LEE ,  Ho In LEE ,  Ju Yeon JANG ,  Je Min PARK ,  Jin Woo HONG

IPC: H01L27/11 ,  H01L27/092 ,  H01L27/108 ,  H01L21/8238 ,  H01L29/10

CPC classification number: H01L27/1104 ,  H01L21/823807 ,  H01L21/823842 ,  H01L27/092 ,  H01L27/10852 ,  H01L27/10867 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10894 ,  H01L29/1029

Abstract: A semiconductor device and method for fabricating the same are provided. The semiconductor device includes a substrate including a cell region, a core region, and a boundary region between the cell region and the core region, a boundary element isolation layer in the boundary region of the substrate to separate the cell region from the core region, a high-k dielectric layer on at least a part of the boundary element isolation layer and the core region of the substrate, a first work function metal pattern comprising a first extension overlapping the boundary element isolation layer on the high-k dielectric layer, and a second work function metal pattern comprising a second extension overlapping the boundary element isolation layer on the first work function metal pattern, wherein a first length of the first extension is different from a second length of the second extension.

公开(公告)号：US20180175038A1

公开(公告)日：2018-06-21

申请号：US15712410

申请日：2017-09-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ho In LEE ,  Dong Oh KIM ,  Seok Han PARK ,  Chan Sic YOON ,  Ki Wook JUNG ,  Jinwoo Augustin HONG ,  Je Min PARK ,  Ki Seok LEE ,  Ju Yeon JANG

IPC: H01L27/108 ,  H01L21/768 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/786 ,  H01L27/12 ,  H01L29/43 ,  H01L29/66

CPC classification number: H01L27/10823 ,  H01L21/762 ,  H01L21/76834 ,  H01L21/823462 ,  H01L21/823468 ,  H01L27/1248 ,  H01L29/432 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7869

Abstract: A method for fabricating a semiconductor device includes forming a device isolation film on a substrate between first and second regions, forming first and second sealing films, such that an etch selectivity of the second sealing film is smaller than that of the first sealing film, patterning the first and second sealing films to expose the second region and a portion of the device isolation film, such that an undercut is defined under a lower surface of the second sealing film, forming a filling film filling the undercut, a thickness of the filling film being thicker on a side surface of the second sealing film than on an upper surface thereof, removing a portion of the filling film to form a filling spacer in the undercut, forming a high-k dielectric film and a metal film on the filling spacer, and patterning the high-k dielectric film and the metal film.