公开(公告)号：US20180226411A1

公开(公告)日：2018-08-09

申请号：US15828934

申请日：2017-12-01

申请人： Samsung Electronics Co., Ltd.

发明人： Ki Wook JUNG ,  Dong Oh KIM ,  Seok Han PARK ,  Chan Sic YOON ,  Ki Seok LEE ,  Ho In LEE ,  Ju Yeon JANG ,  Je Min PARK ,  Jin Woo HONG

IPC分类号： H01L27/11 ,  H01L27/092 ,  H01L27/108 ,  H01L21/8238 ,  H01L29/10

CPC分类号： H01L27/1104 ,  H01L21/823807 ,  H01L21/823842 ,  H01L27/092 ,  H01L27/10852 ,  H01L27/10867 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10894 ,  H01L29/1029

摘要： A semiconductor device and method for fabricating the same are provided. The semiconductor device includes a substrate including a cell region, a core region, and a boundary region between the cell region and the core region, a boundary element isolation layer in the boundary region of the substrate to separate the cell region from the core region, a high-k dielectric layer on at least a part of the boundary element isolation layer and the core region of the substrate, a first work function metal pattern comprising a first extension overlapping the boundary element isolation layer on the high-k dielectric layer, and a second work function metal pattern comprising a second extension overlapping the boundary element isolation layer on the first work function metal pattern, wherein a first length of the first extension is different from a second length of the second extension.

公开(公告)号：US20190252393A1

公开(公告)日：2019-08-15

申请号：US16391888

申请日：2019-04-23

申请人： Samsung Electronics Co., Ltd.

发明人： Ki Wook JUNG ,  Dong Oh KIM ,  Seok Han PARK ,  Chan Sic YOON ,  Ki Seok LEE ,  Ho ln LEE ,  Ju Yeon JANG ,  Je Min PARK ,  Jin Woo HONG

IPC分类号： H01L27/11 ,  H01L27/108 ,  H01L29/10 ,  H01L21/8238

摘要： A semiconductor device and method for fabricating the same are provided. The semiconductor device includes a substrate including a cell region, a core region, and a boundary region between the cell region and the core region, a boundary element isolation layer in the boundary region of the substrate to separate the cell region from the core region, a high-k dielectric layer on at least a part of the boundary element isolation layer and the core region of the substrate, a first work function metal pattern comprising a first extension overlapping the boundary element isolation layer on the high-k dielectric layer, and a second work function metal pattern comprising a second extension overlapping the boundary element isolation layer on the first work function metal pattern, wherein a first length of the first extension is different from a second length of the second extension.

公开(公告)号：US20170278847A1

公开(公告)日：2017-09-28

申请号：US15461726

申请日：2017-03-17

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Dong Oh KIM ,  Chan Sic YOON ,  Ki Seok LEE ,  Yong Jae KIM

IPC分类号： H01L27/108 ,  H01L23/528 ,  H01L29/06

CPC分类号： H01L27/10814 ,  H01L23/528 ,  H01L27/10844 ,  H01L27/10852 ,  H01L29/0696

摘要： A semiconductor device includes a substrate including a cell area and a background area, the background area surrounding the cell area, a plurality of active patterns in the cell area along a first direction, the active patterns being defined by a device isolation layer, and a background pattern filling the background area to surround the cell area, wherein the active patterns include a first active pattern most adjacent to an edge of the cell area, and a second active pattern separated from the first active pattern in a second direction intersecting the first direction, the second active pattern being separated from the background area.

公开(公告)号：US20180175038A1

公开(公告)日：2018-06-21

申请号：US15712410

申请日：2017-09-22

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Ho In LEE ,  Dong Oh KIM ,  Seok Han PARK ,  Chan Sic YOON ,  Ki Wook JUNG ,  Jinwoo Augustin HONG ,  Je Min PARK ,  Ki Seok LEE ,  Ju Yeon JANG

IPC分类号： H01L27/108 ,  H01L21/768 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/786 ,  H01L27/12 ,  H01L29/43 ,  H01L29/66

CPC分类号： H01L27/10823 ,  H01L21/762 ,  H01L21/76834 ,  H01L21/823462 ,  H01L21/823468 ,  H01L27/1248 ,  H01L29/432 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7869

摘要： A method for fabricating a semiconductor device includes forming a device isolation film on a substrate between first and second regions, forming first and second sealing films, such that an etch selectivity of the second sealing film is smaller than that of the first sealing film, patterning the first and second sealing films to expose the second region and a portion of the device isolation film, such that an undercut is defined under a lower surface of the second sealing film, forming a filling film filling the undercut, a thickness of the filling film being thicker on a side surface of the second sealing film than on an upper surface thereof, removing a portion of the filling film to form a filling spacer in the undercut, forming a high-k dielectric film and a metal film on the filling spacer, and patterning the high-k dielectric film and the metal film.

公开(公告)号：US20170213724A1

公开(公告)日：2017-07-27

申请号：US15291415

申请日：2016-10-12

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Chan Sic YOON ,  Ki Seok LEE ,  Dong Oh KIM

IPC分类号： H01L21/027

CPC分类号： H01L21/0276 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/32139 ,  H01L21/823431 ,  H01L21/823481

摘要： A method for manufacturing a semiconductor device includes forming features of a first mold pattern on a substrate including a first region and a second region, and forming a first insulation layer covering the first mold pattern from the first region to the second region. The method further includes forming a photoresist pattern on the first insulation layer in the second region, forming a second insulation layer covering the first insulation layer in the first region and the photoresist pattern in the second region from the first region to the second region, etching the second insulation layer, removing the photoresist pattern, and forming a first double patterning technology pattern having a first width in the first region and a second DPT pattern having a second width in the second region, wherein the second width is different from the first width.

公开(公告)号：US20210246044A1

公开(公告)日：2021-08-12

申请号：US17229031

申请日：2021-04-13

申请人： Samsung Electronics Co., Ltd.

发明人： Ki Wook JUNG ,  Dong Oh KIM ,  Seok Han PARK ,  Chan Sic YOON ,  Ki Seok LEE ,  Ho In LEE ,  Ju Yeon JANG ,  Je Min PARK ,  Jin Woo HONG

IPC分类号： C01G23/053

摘要： A semiconductor device and method for fabricating the same are provided. The semiconductor device includes a substrate including a cell region, a core region, and a boundary region between the cell region and the core region, a boundary element isolation layer in the boundary region of the substrate to separate the cell region from the core region, a high-k dielectric layer on at least a part of the boundary element isolation layer and the core region of the substrate, a first work function metal pattern comprising a first extension overlapping the boundary element isolation layer on the high-k dielectric layer, and a second work function metal pattern comprising a second extension overlapping the boundary element isolation layer on the first work function metal pattern, wherein a first length of the first extension is different from a second length of the second extension.

公开(公告)号：US20180158718A1

公开(公告)日：2018-06-07

申请号：US15667118

申请日：2017-08-02

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： DONG RYUL LEE ,  Joong Chan SHIN ,  Dong Jun LEE ,  Ho Ouk LEE ,  Ji Min CHOI ,  Ji Young KIM ,  Chan Sic YOON ,  Chang Hyun CHO

IPC分类号： H01L21/764 ,  H01L21/768 ,  H01L29/06 ,  H01L29/49 ,  H01L23/522

CPC分类号： H01L21/764 ,  H01L21/7682 ,  H01L21/76897 ,  H01L23/522 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10894 ,  H01L29/0649 ,  H01L29/4983

摘要： A method for fabricating a semiconductor device includes providing a substrate including a cell region including a bit line structure, a bit line spacer and a lower electrode and a peripheral circuit region including first to third impurity regions, forming an interlayer insulating film on the peripheral circuit region, forming a first metal layer on the interlayer insulating film, forming a first trench and a second trench in the first metal layer between the first and second impurity regions, the second trench is disposed between the second and third impurity regions and exposes the interlayer insulating film, forming a first capping pattern on the first trench to form an air gap in the first trench, filling the second trench with a first insulating material, and forming, on the first metal layer, a contact connected to the third impurity region.

公开(公告)号：US20170309469A1

公开(公告)日：2017-10-26

申请号：US15381135

申请日：2016-12-16

申请人： Samsung Electronics Co., Ltd.,

发明人： Chan Sic YOON ,  Ki Seok LEE ,  Dong Oh KIM ,  Yong Jae KIM

IPC分类号： H01L21/027 ,  G03F1/38 ,  H01L21/02

CPC分类号： H01L21/027 ,  G03F1/38 ,  H01L21/02107 ,  H01L21/02697 ,  H01L27/0207 ,  H01L27/10888

摘要： Methods for manufacturing a semiconductor device include forming a gate line extending in a first direction in a substrate, and an impurity region on a side surface of the gate line, forming an insulating film pattern on the substrate, the insulating film pattern extending in the first direction and comprising a first through-hole that is configured to expose the impurity region, forming a barrier metal layer on the first through-hole, forming a conductive line contact that fills the first through-hole and that is electrically connected to the impurity region, forming a first mask pattern on the conductive line contact and the insulating film pattern, the first mask pattern extending in a second direction that is different from the first direction and the first mask pattern comprising a first opening, and removing corners of the barrier metal layer by partially etching the barrier metal layer.

公开(公告)号：US20170194261A1

公开(公告)日：2017-07-06

申请号：US15258138

申请日：2016-09-07

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Chan Sic YOON ,  Ki Seok LEE

IPC分类号： H01L23/535 ,  H01L29/423 ,  H01L29/06

CPC分类号： H01L23/535 ,  H01L23/485 ,  H01L27/10814 ,  H01L29/0649 ,  H01L29/4236

摘要： A semiconductor device includes a first contact plug on a substrate, a first lower electrode disposed on the first contact plug and extended in a thickness direction of the substrate, a first supporter pattern on the first lower electrode and including an upper surface and a lower surface, the upper surface of the first supporter pattern being higher than a top surface of the first lower electrode, a dielectric film on the first lower electrode, the upper surface of the first supporter pattern and the lower surface of the first supporter pattern and an upper electrode disposed on the dielectric film.