公开(公告)号：US20180226411A1

公开(公告)日：2018-08-09

申请号：US15828934

申请日：2017-12-01

申请人： Samsung Electronics Co., Ltd.

发明人： Ki Wook JUNG ,  Dong Oh KIM ,  Seok Han PARK ,  Chan Sic YOON ,  Ki Seok LEE ,  Ho In LEE ,  Ju Yeon JANG ,  Je Min PARK ,  Jin Woo HONG

IPC分类号： H01L27/11 ,  H01L27/092 ,  H01L27/108 ,  H01L21/8238 ,  H01L29/10

CPC分类号： H01L27/1104 ,  H01L21/823807 ,  H01L21/823842 ,  H01L27/092 ,  H01L27/10852 ,  H01L27/10867 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10894 ,  H01L29/1029

摘要： A semiconductor device and method for fabricating the same are provided. The semiconductor device includes a substrate including a cell region, a core region, and a boundary region between the cell region and the core region, a boundary element isolation layer in the boundary region of the substrate to separate the cell region from the core region, a high-k dielectric layer on at least a part of the boundary element isolation layer and the core region of the substrate, a first work function metal pattern comprising a first extension overlapping the boundary element isolation layer on the high-k dielectric layer, and a second work function metal pattern comprising a second extension overlapping the boundary element isolation layer on the first work function metal pattern, wherein a first length of the first extension is different from a second length of the second extension.

公开(公告)号：US20210246044A1

公开(公告)日：2021-08-12

申请号：US17229031

申请日：2021-04-13

申请人： Samsung Electronics Co., Ltd.

发明人： Ki Wook JUNG ,  Dong Oh KIM ,  Seok Han PARK ,  Chan Sic YOON ,  Ki Seok LEE ,  Ho In LEE ,  Ju Yeon JANG ,  Je Min PARK ,  Jin Woo HONG

IPC分类号： C01G23/053

摘要： A semiconductor device and method for fabricating the same are provided. The semiconductor device includes a substrate including a cell region, a core region, and a boundary region between the cell region and the core region, a boundary element isolation layer in the boundary region of the substrate to separate the cell region from the core region, a high-k dielectric layer on at least a part of the boundary element isolation layer and the core region of the substrate, a first work function metal pattern comprising a first extension overlapping the boundary element isolation layer on the high-k dielectric layer, and a second work function metal pattern comprising a second extension overlapping the boundary element isolation layer on the first work function metal pattern, wherein a first length of the first extension is different from a second length of the second extension.

公开(公告)号：US20200035499A1

公开(公告)日：2020-01-30

申请号：US16250180

申请日：2019-01-17

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Sung-Min PARK ,  Se Myeong JANG ,  Bong Soo KIM ,  Je Min PARK

IPC分类号： H01L21/308 ,  H01L21/033

摘要： A method includes forming hard mask patterns by depositing a support mask layer, a polycrystalline silicon layer, and a hard mask layer on a substrate and etching the hard mask layer, forming pre-polycrystalline silicon patterns by etching the polycrystalline silicon layer using the hard mask patterns as an etch mask, oxidizing side surfaces of the pre-polycrystalline silicon patterns to form polycrystalline silicon patterns and a silicon oxide layer, forming spacer patterns covering sides of the silicon oxide layer, forming a sacrificial layer on a top surface of the support mask layer to cover the silicon oxide layer and the spacer patterns, etching the sacrificial layer and the silicon oxide layer, forming support mask patterns by etching the support mask layer using the polycrystalline silicon patterns and the spacer patterns as an etch mask, and forming activation pins by etching the substrate using the support mask patterns as an etch mask.

公开(公告)号：US20210013046A1

公开(公告)日：2021-01-14

申请号：US17032356

申请日：2020-09-25

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Sung-Min PARK ,  Se Myeong JANG ,  Bong Soo KIM ,  Je Min PARK

IPC分类号： H01L21/308 ,  H01L21/033

摘要： A method includes forming hard mask patterns by depositing a support mask layer, a polycrystalline silicon layer, and a hard mask layer on a substrate and etching the hard mask layer, forming pre-polycrystalline silicon patterns by etching the polycrystalline silicon layer using the hard mask patterns as an etch mask, oxidizing side surfaces of the pre-polycrystalline silicon patterns to form polycrystalline silicon patterns and a silicon oxide layer, forming spacer patterns covering sides of the silicon oxide layer, forming a sacrificial layer on a top surface of the support mask layer to cover the silicon oxide layer and the spacer patterns, etching the sacrificial layer and the silicon oxide layer, forming support mask patterns by etching the support mask layer using the polycrystalline silicon patterns and the spacer patterns as an etch mask, and forming activation pins by etching the substrate using the support mask patterns as an etch mask.

公开(公告)号：US20190252393A1

公开(公告)日：2019-08-15

申请号：US16391888

申请日：2019-04-23

申请人： Samsung Electronics Co., Ltd.

发明人： Ki Wook JUNG ,  Dong Oh KIM ,  Seok Han PARK ,  Chan Sic YOON ,  Ki Seok LEE ,  Ho ln LEE ,  Ju Yeon JANG ,  Je Min PARK ,  Jin Woo HONG

IPC分类号： H01L27/11 ,  H01L27/108 ,  H01L29/10 ,  H01L21/8238

摘要： A semiconductor device and method for fabricating the same are provided. The semiconductor device includes a substrate including a cell region, a core region, and a boundary region between the cell region and the core region, a boundary element isolation layer in the boundary region of the substrate to separate the cell region from the core region, a high-k dielectric layer on at least a part of the boundary element isolation layer and the core region of the substrate, a first work function metal pattern comprising a first extension overlapping the boundary element isolation layer on the high-k dielectric layer, and a second work function metal pattern comprising a second extension overlapping the boundary element isolation layer on the first work function metal pattern, wherein a first length of the first extension is different from a second length of the second extension.

公开(公告)号：US20190088659A1

公开(公告)日：2019-03-21

申请号：US16183826

申请日：2018-11-08

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Ki Seok LEE ,  Jeong Seop SHIM ,  Mi Na LEE ,  Augustin Jinwoo HONG ,  Je Min PARK ,  Hye Jin SEONG ,  Seung Min OH ,  Do Yeong LEE ,  Ji Seung LEE ,  Jin Seong LEE

IPC分类号： H01L27/108

CPC分类号： H01L27/10885 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10855 ,  H01L27/10891

摘要： A semiconductor device includes a substrate including spaced-apart active regions, and device isolating regions isolating the active regions from each other, and a pillar array pattern including a plurality of pillar patterns overlapping the active regions, the plurality of pillar patterns being spaced apart from each other at an equal distance in a first direction and in a second direction intersecting the first direction, wherein the plurality of pillar patterns include first pillar patterns and second pillar patterns disposed alternatingly in the first direction and in the second direction, a shape of a horizontal cross section of the first pillar patterns being different from a shape of a horizontal cross section of the second pillar patterns.

公开(公告)号：US20180175038A1

公开(公告)日：2018-06-21

申请号：US15712410

申请日：2017-09-22

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Ho In LEE ,  Dong Oh KIM ,  Seok Han PARK ,  Chan Sic YOON ,  Ki Wook JUNG ,  Jinwoo Augustin HONG ,  Je Min PARK ,  Ki Seok LEE ,  Ju Yeon JANG

IPC分类号： H01L27/108 ,  H01L21/768 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/786 ,  H01L27/12 ,  H01L29/43 ,  H01L29/66

CPC分类号： H01L27/10823 ,  H01L21/762 ,  H01L21/76834 ,  H01L21/823462 ,  H01L21/823468 ,  H01L27/1248 ,  H01L29/432 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7869

摘要： A method for fabricating a semiconductor device includes forming a device isolation film on a substrate between first and second regions, forming first and second sealing films, such that an etch selectivity of the second sealing film is smaller than that of the first sealing film, patterning the first and second sealing films to expose the second region and a portion of the device isolation film, such that an undercut is defined under a lower surface of the second sealing film, forming a filling film filling the undercut, a thickness of the filling film being thicker on a side surface of the second sealing film than on an upper surface thereof, removing a portion of the filling film to form a filling spacer in the undercut, forming a high-k dielectric film and a metal film on the filling spacer, and patterning the high-k dielectric film and the metal film.

公开(公告)号：US20170200725A1

公开(公告)日：2017-07-13

申请号：US15275827

申请日：2016-09-26

申请人： Samsung Electronics Co., Ltd.

发明人： Ki Seok LEE ,  Jeong Seop SHIM ,  Mi Na LEE ,  Augustin Jinwoo HONG ,  Je Min PARK ,  Hye Jin SEONG ,  Seung Min OH ,  Do Yeong LEE ,  Ji Seung LEE ,  Jin Seong LEE

IPC分类号： H01L27/108

CPC分类号： H01L27/10885 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10855 ,  H01L27/10891

摘要： A semiconductor device includes a substrate including spaced-apart active regions, and device isolating regions isolating the active regions from each other, and a pillar array pattern including a plurality of pillar patterns overlapping the active regions, the plurality of pillar patterns being spaced apart from each other at an equal distance in a first direction and in a second direction intersecting the first direction, wherein the plurality of pillar patterns include first pillar patterns and second pillar patterns disposed alternatingly in the first direction and in the second direction, a shape of a horizontal cross section of the first pillar patterns being different from a shape of a horizontal cross section of the second pillar patterns.