公开(公告)号：US20230389258A1

公开(公告)日：2023-11-30

申请号：US18201465

申请日：2023-05-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eo Jin Lee ,  Ho Young Tang ,  Tae-Hyung Kim ,  Dae Young Moon

IPC: H10B10/00

CPC classification number: H10B10/125

Abstract: An integrated circuit includes a static random access memory (SRAM) device. The SRAM device includes an SRAM unit cell that includes a first output node to which a first pull-up transistor, a first pull-down transistor, and a second pull-down transistor are commonly connected, and a second output node to which a second pull-up transistor, a third pull-down transistor, and a fourth pull-down transistor are commonly connected. The first output node is connected to a first gate electrode, a second gate electrode, a first connection wiring line, a first node formation pattern, and a first active contact, and a layout of the first output node, the first gate electrode, the second gate electrode, the first connection wiring line, the first node formation pattern, and the first active contact forms a first fork shape.

公开(公告)号：US20240321344A1

公开(公告)日：2024-09-26

申请号：US18612372

申请日：2024-03-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-Hyun Choi ,  Ho Young Tang ,  Eo Jin Lee ,  Tae-Hyung Kim ,  Yu Tak Jeong

IPC: G11C11/412 ,  G11C11/419 ,  H01L23/528 ,  H10B10/00

CPC classification number: G11C11/412 ,  H01L23/528 ,  H10B10/12 ,  G11C11/419

Abstract: A memory device is provided. The memory device includes a memory cell array including a plurality of memory cells arranged in a plurality of columns and rows and including first and second memory cells in a same column and different rows, the plurality of columns intersecting the plurality of rows in a plan view, a first bit line transistor electrically connected between the first memory cell and a first bit line metal line and a second bit line transistor electrically connected between the second memory cell and a second bit line metal line, wherein the first bit line metal line is on an upper surface of the memory cell array, and the second bit line metal line is on a lower surface of the memory cell array opposite the upper surface of the memory cell array.