公开(公告)号：US20230389258A1

公开(公告)日：2023-11-30

申请号：US18201465

申请日：2023-05-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eo Jin Lee ,  Ho Young Tang ,  Tae-Hyung Kim ,  Dae Young Moon

IPC: H10B10/00

CPC classification number: H10B10/125

Abstract: An integrated circuit includes a static random access memory (SRAM) device. The SRAM device includes an SRAM unit cell that includes a first output node to which a first pull-up transistor, a first pull-down transistor, and a second pull-down transistor are commonly connected, and a second output node to which a second pull-up transistor, a third pull-down transistor, and a fourth pull-down transistor are commonly connected. The first output node is connected to a first gate electrode, a second gate electrode, a first connection wiring line, a first node formation pattern, and a first active contact, and a layout of the first output node, the first gate electrode, the second gate electrode, the first connection wiring line, the first node formation pattern, and the first active contact forms a first fork shape.

公开(公告)号：US12219753B2

公开(公告)日：2025-02-04

申请号：US18538358

申请日：2023-12-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin Won Ma ,  Ja Min Koo ,  Dae Young Moon ,  Kyu Wan Kim ,  Bong Hyun Kim ,  Young Seok Kim

IPC: H10B12/00

Abstract: A semiconductor memory device includes a substrate including an element separation film and an active region defined by the element separation film, a bit line structure on the substrate, a trench in the element separation film and the active region, the trench on at least one side of the bit line structure and including a first portion in the element separation film and a second portion in the active region, a bottom face of the first portion placed above a bottom face of the second portion, a single crystal storage contact filling the trench, and an information storage element electrically connected to the single crystal storage contact.

公开(公告)号：US11877443B2

公开(公告)日：2024-01-16

申请号：US17355451

申请日：2021-06-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin Won Ma ,  Ja Min Koo ,  Dae Young Moon ,  Kyu Wan Kim ,  Bong Hyun Kim ,  Young Seok Kim

IPC: H10B12/00

CPC classification number: H10B12/485 ,  H10B12/37

Abstract: A semiconductor memory device includes a substrate including an element separation film and an active region defined by the element separation film, a bit line structure on the substrate, a trench in the element separation film and the active region, the trench on at least one side of the bit line structure and including a first portion in the element separation film and a second portion in the active region, a bottom face of the first portion placed above a bottom face of the second portion, a single crystal storage contact filling the trench, and an information storage element electrically connected to the single crystal storage contact.