Method controlling deep power down mode in multi-port semiconductor memory
    1.
    发明授权
    Method controlling deep power down mode in multi-port semiconductor memory 有权
    在多端口半导体存储器中控制深度掉电模式的方法

    公开(公告)号:US08675440B2

    公开(公告)日:2014-03-18

    申请号:US13754950

    申请日:2013-01-31

    CPC classification number: G11C5/148 G11C5/144 G11C5/147 G11C8/16

    Abstract: A method of controlling a deep power down mode in a multi-port semiconductor memory having a plurality of ports connected to a plurality of processors includes controlling the deep power down mode in the multi-port semiconductor memory such that activation/deactivation of the deep power down mode are determined in accordance with signals applied through various ports in the plurality of ports.

    Abstract translation: 在具有连接到多个处理器的多个端口的多端口半导体存储器中控制深度掉电模式的方法包括控制多端口半导体存储器中的深度掉电模式,使得深度功率的激活/去激活 根据通过多个端口中的各个端口施加的信号确定下降模式。

    APPARATUS AND METHOD FOR IDENTIFYING APPLICATION USING PACKET IN COMMUNICATION SYSTEM
    2.
    发明申请
    APPARATUS AND METHOD FOR IDENTIFYING APPLICATION USING PACKET IN COMMUNICATION SYSTEM 审中-公开
    用于识别在通信系统中使用分组的应用的装置和方法

    公开(公告)号:US20130170377A1

    公开(公告)日:2013-07-04

    申请号:US13734044

    申请日:2013-01-04

    CPC classification number: H04L69/22

    Abstract: An apparatus and a method for identify an application to which a packet flow belongs in a communication system. In the method, characteristic information of a first application is selected. Bit lines of a position designated by a mask included in the characteristic information are examined from packets transferred via the packet flow. A ratio of the number of examination results of coincidence to the number of all input packets is calculated. When the ratio exceeds a first threshold included in the characteristic information, it is determined that the packet flow belongs to the first application.

    Abstract translation: 用于识别分组流在通信系统中所属的应用的装置和方法。 在该方法中,选择第一应用的特征信息。 从由分组流传送的分组检查由特征信息中包括的掩码指定的位置的位线。 计算一致性检查结果与所有输入数据包数的比例。 当比率超过包括在特征信息中的第一阈值时,确定分组流属于第一应用。

    MEMORY DEVICE INCLUDING ANTIFUSE MEMORY CELL ARRAY AND MEMORY SYSTEM INCLUDING THE MEMORY DEVICE
    4.
    发明申请
    MEMORY DEVICE INCLUDING ANTIFUSE MEMORY CELL ARRAY AND MEMORY SYSTEM INCLUDING THE MEMORY DEVICE 审中-公开
    包括防病毒存储器单元阵列和包含存储器件的存储器系统的存储器件

    公开(公告)号:US20130294141A1

    公开(公告)日:2013-11-07

    申请号:US13803612

    申请日:2013-03-14

    CPC classification number: G11C17/18 G11C17/16

    Abstract: A memory device includes a memory cell array, a column decoder, and a row decoder. The row decoder includes a first word line driver and a second word line driver. The first word line driver is configured to electrically coupled to a first set of antifuse memory cells coupled to a first word line. The second word line driver is configured to electrically coupled to a second set of antifuse memory cells coupled to a second word line. The first set of antifuse memory cells are arranged in first and third rows of the memory cell array, and the second set of antifuse memory cells are arranged in second and fourth rows of the memory cell array. The second row is arranged between the first and third rows.

    Abstract translation: 存储器件包括存储单元阵列,列解码器和行解码器。 行解码器包括第一字线驱动器和第二字线驱动器。 第一字线驱动器被配置为电耦合到耦合到第一字线的第一组反熔丝存储器单元。 第二字线驱动器被配置为电耦合到耦合到第二字线的第二组反熔丝存储器单元。 第一组反熔丝存储单元布置在存储单元阵列的第一行和第三行中,第二组反熔丝存储单元布置在存储单元阵列的第二行和第四行中。 第二排布置在第一行和第三行之间。

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